高功率密度3D高性能计算架构双面嵌入式液冷的热优化

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-05-03 DOI:10.1016/j.mejo.2025.106714

Yunting Liu , Rong Fu , Meiying Su , Jun Li , Chuan Chen , Fengman Liu

{"title":"高功率密度3D高性能计算架构双面嵌入式液冷的热优化","authors":"Yunting Liu , Rong Fu , Meiying Su , Jun Li , Chuan Chen , Fengman Liu","doi":"10.1016/j.mejo.2025.106714","DOIUrl":null,"url":null,"abstract":"<div><div>This study presents a thermal resistance analysis framework for 3D High-Performance Computing (HPC) architectures, evaluating memory-on-logic (MOL) and logic-on-memory (LOM) configurations with varying power delivery networks and cooling strategies. We develop an analytical model to identify temperature control limits under extreme heat flux and propose optimized cooling solutions. A novel TSV-compatible embedded microchannel fabrication process achieves a 34.21 % TSV-available silicon area ratio. Thermal simulations show that dual-sided cooling (DSC) reduces temperature rise by 72.2 % under 100 W power, with less than 10K deviation from experimental results. The optimized design maintains 41.3 kPa inlet pressure at 4.2 L/h flow rate, offering effective thermal management for high-power-density 3D HPC systems.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"161 ","pages":"Article 106714"},"PeriodicalIF":1.9000,"publicationDate":"2025-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Thermal optimization of dual-sided embedded liquid cooling for high-power-density 3D HPC architectures\",\"authors\":\"Yunting Liu , Rong Fu , Meiying Su , Jun Li , Chuan Chen , Fengman Liu\",\"doi\":\"10.1016/j.mejo.2025.106714\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>This study presents a thermal resistance analysis framework for 3D High-Performance Computing (HPC) architectures, evaluating memory-on-logic (MOL) and logic-on-memory (LOM) configurations with varying power delivery networks and cooling strategies. We develop an analytical model to identify temperature control limits under extreme heat flux and propose optimized cooling solutions. A novel TSV-compatible embedded microchannel fabrication process achieves a 34.21 % TSV-available silicon area ratio. Thermal simulations show that dual-sided cooling (DSC) reduces temperature rise by 72.2 % under 100 W power, with less than 10K deviation from experimental results. The optimized design maintains 41.3 kPa inlet pressure at 4.2 L/h flow rate, offering effective thermal management for high-power-density 3D HPC systems.</div></div>\",\"PeriodicalId\":49818,\"journal\":{\"name\":\"Microelectronics Journal\",\"volume\":\"161 \",\"pages\":\"Article 106714\"},\"PeriodicalIF\":1.9000,\"publicationDate\":\"2025-05-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronics Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S1879239125001638\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239125001638","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

摘要

本研究提出了3D高性能计算（HPC）架构的热阻分析框架，评估了不同电力输送网络和冷却策略下的内存-on-logic （MOL）和逻辑-on-memory （LOM）配置。我们开发了一个分析模型来确定极端热通量下的温度控制极限，并提出优化的冷却解决方案。一种新的兼容tsv的嵌入式微通道制造工艺实现了34.21%的tsv可用硅面积比。热模拟结果表明，在100 W功率下，双面冷却（DSC）可降低72.2%的温升，与实验结果偏差小于10K。优化后的设计在4.2 L/h流量下仍能保持41.3 kPa的进口压力，为高功率密度3D高性能计算系统提供有效的热管理。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Thermal optimization of dual-sided embedded liquid cooling for high-power-density 3D HPC architectures

This study presents a thermal resistance analysis framework for 3D High-Performance Computing (HPC) architectures, evaluating memory-on-logic (MOL) and logic-on-memory (LOM) configurations with varying power delivery networks and cooling strategies. We develop an analytical model to identify temperature control limits under extreme heat flux and propose optimized cooling solutions. A novel TSV-compatible embedded microchannel fabrication process achieves a 34.21 % TSV-available silicon area ratio. Thermal simulations show that dual-sided cooling (DSC) reduces temperature rise by 72.2 % under 100 W power, with less than 10K deviation from experimental results. The optimized design maintains 41.3 kPa inlet pressure at 4.2 L/h flow rate, offering effective thermal management for high-power-density 3D HPC systems.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.