Microelectronics Journal最新文献_第8页

Investigation on palladium gate electrode-based SOI junctionless FET for hydrogen gas sensing 基于钯栅电极的氢气传感 SOI 无结 FET 研究

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-18 DOI: 10.1016/j.mejo.2024.106312

{"title":"Investigation on palladium gate electrode-based SOI junctionless FET for hydrogen gas sensing","authors":"","doi":"10.1016/j.mejo.2024.106312","DOIUrl":"10.1016/j.mejo.2024.106312","url":null,"abstract":"<div>This study provides a comprehensive investigation on palladium (Pd) gate electrode-based silicon on insulator (SOI) junctionless field-effect transistor (JLFET) for hydrogen gas (H2) sensing (Pd–SOI-JLFET). The device has a gate dielectric stack consisting of silicon dioxide (SiO2) and hafnium dioxide (HfO2). An extensive analysis was conducted to detect and identify the presence of hydrogen gas by examining several electrical characteristics such as drain current (IDS), transconductance (gm), output conductance (gd), energy band diagram (E), gate-to-source capacitance (CGS), and surface potential (Φs). Furthermore, a comprehensive investigation was conducted to examine the impact of the presence of H2 gas and variations in temperature on important parameters associated with the short channel effects (SCEs) including off-state current (IOFF), on-state current (ION), subthreshold swing (SS) and threshold voltage (Vth). In addition, the sensitivity analysis of the off-state current (IOFF) by considering process variation effect has been done. Sensitivity is also calculated at various temperatures for the detection of hydrogen gas molecule. At the temperature of 300K, the sensitivity values were obtained as 1.50083, 3.21754, 27.71483, 152.39617 and 2052.8 for pressure values 10−14 Torr, 10−13 Torr, 10−12 Torr, 10−11 Torr and 10−10 Torr, respectively. This analysis provides a thorough examination of the performance and efficacy of the Pd–SOI-JLFET hydrogen gas sensor highlighting its potential for a wide range of hydrogen sensing applications.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141729194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Unified multifunctional-reconfigurable architecture for device-circuit co-design 用于器件-电路协同设计的多功能可配置统一架构

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-18 DOI: 10.1016/j.mejo.2024.106329

{"title":"Unified multifunctional-reconfigurable architecture for device-circuit co-design","authors":"","doi":"10.1016/j.mejo.2024.106329","DOIUrl":"10.1016/j.mejo.2024.106329","url":null,"abstract":"<div>In this article, we propose a novel unified device-circuit co-design for functional scalability and diversifiability within the same footprint. The proposed design comprises two L-shaped NMOS monolithically integrated with two L-shaped PMOS utilizing common silicon reservoir with charge-plasma (CP) induced source and drain regions. The CP regions are induced by choosing appropriate work functions for the metal electrodes using calibrated TCAD simulations. Through source-drain interchangeability among individual transistors and appropriate signal bias, we have demonstrated the possible reconfigurations of the proposed single architecture to perform various device and/or circuit level operations concurrently/separately. For device level analyses, we realized concurrent NMOS and PMOS in single-channel and/or dual-channel configurations. Further, for circuit level analyses, we realized a CMOS inverter in addition to an NMOS and a PMOS, all three operating independently. Next, we demonstrated two independent inverters with possible realization of a buffer. Lastly, we present NAND and NOR Gates, each in two possible configurations, obtained through the proposed single-device architecture.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141731791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 18-bit 1-MS/s fully-differential SAR ADC with digital calibration achieving 96.1 dB SNDR 具有数字校准功能的 18 位 1-MS/s 全差分 SAR ADC，实现 96.1 dB SNDR

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-18 DOI: 10.1016/j.mejo.2024.106297

{"title":"A 18-bit 1-MS/s fully-differential SAR ADC with digital calibration achieving 96.1 dB SNDR","authors":"","doi":"10.1016/j.mejo.2024.106297","DOIUrl":"10.1016/j.mejo.2024.106297","url":null,"abstract":"<div>This paper presents a 18-bit 1 MS/s fully-differential Successive-Approximation-Register Analog-to-Digital Converter (SAR ADC) achieving an ENOB of 15.7-bit. To achieve higher performance, a differential DAC utilizing both split and monotonic switching timing is designed. For both dynamic and static performance improvement, five techniques are proposed. First, a foreground digital self-calibration method based on normalized-full-scale-referencing is described to eliminate the capacitor mismatch errors. L-segment capacitors are utilized to measure and calculate the bit weights of other capacitors. Second, a DNL enhancement technique is presented. The fractional capacitors are used to subtract an analog voltage from the DAC before the conversion is finished, which further improve the ADC performance. Third, an adaptive-tracking-extra-bit-trail together with comparator noise extraction and correction for further accuracy enhancement is proposed. Forth, a harmonic calibration technique, which can efficiently attenuate 2-order and 3-order harmonic is introduced. Fifth, a comparator with ultra-low noise and offset is designed to meet the 18-bit 1-MS/s ADC. The ADC is fabricated in a 0.18-μm 5-V CMOS process. It measures a 96.1 dB SNDR and a 110.7 dB SFDR. The DNL and INL are within ±0.32 LSB and ±0.5 LSB, respectively. The overall power consumption of ADC core, drawn from the 5 V power supply, is 45 mW.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141848137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analytical modeling of threshold voltage and on-resistance in multi-barrier E-mode MISHEMT with gate-recess and field-plates 带栅极前置和场板的多势垒 E-Mode MISHEMT 的阈值电压和导通电阻的分析建模

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-18 DOI: 10.1016/j.mejo.2024.106318

{"title":"Analytical modeling of threshold voltage and on-resistance in multi-barrier E-mode MISHEMT with gate-recess and field-plates","authors":"","doi":"10.1016/j.mejo.2024.106318","DOIUrl":"10.1016/j.mejo.2024.106318","url":null,"abstract":"<div>This work presents an analytical model for threshold voltage and On-resistance of multi barrier Metal–Insulator–Semiconductor High-Electron-Mobility-Transistor (MISHEMT) with gate-recess and field-plates. The device featuring a high two-dimensional electron-gas (2DEG) density in the channel region. The primary objectives of this device are to achieve a high threshold voltage (<math><mrow><msub><mi>V</mi><mrow><mi>t</mi><mi>h</mi></mrow></msub></mrow></math>) and enhance electron mobility with specific low ON-resistance (<math><mrow><msub><mi>R</mi><mrow><mi>o</mi><mi>n</mi><mo>_</mo><mi>s</mi><mi>p</mi></mrow></msub></mrow></math>) by mitigating the degradation effects arising from scattering and interface-charges. Also, a physics based analytical model for <math><mrow><msub><mi>V</mi><mrow><mi>t</mi><mi>h</mi></mrow></msub></mrow></math> and 2DEG charge density at upper and lower channels is presented. This model is validated by comparing with TCAD numerical simulations and are well matched. The proposed MISHEMT demonstrates improved electron mobility in the lower channel of 1260 <math><mrow><msup><mrow><mi>c</mi><mi>m</mi></mrow><mn>2</mn></msup><mo>/</mo><mi>V</mi><mo>.</mo><mi>s</mi></mrow></math>, <math><mrow><msub><mi>V</mi><mrow><mi>t</mi><mi>h</mi></mrow></msub></mrow></math> of ∼2.6 V and <math><mrow><msub><mi>R</mi><mrow><mi>o</mi><mi>n</mi><mo>_</mo><mi>s</mi><mi>p</mi></mrow></msub></mrow></math> is minimized by 33 % in contrast with a conventional MISHEMT. Additionally, the proposed MISHEMT becomes a promising device for achieving both high threshold voltage and mobility which are required for power semiconductor devices.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141841753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A transient-enhanced output-capacitorless LDO regulator with non-inverting pull–push gain stage 具有非反相推挽增益级的瞬态增强型输出无电容 LDO 稳压器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-18 DOI: 10.1016/j.mejo.2024.106299

{"title":"A transient-enhanced output-capacitorless LDO regulator with non-inverting pull–push gain stage","authors":"","doi":"10.1016/j.mejo.2024.106299","DOIUrl":"10.1016/j.mejo.2024.106299","url":null,"abstract":"<div>A novel non-inverting pull–push gain stage output-capacitorless low-dropout regulator (OCL-LDO) is introduced, designed specifically for power management of system-on-chip (SoC). The incorporation of an innovative non-inverting gain stage (NIGS) serves to shift the non-dominant parasitic poles to higher frequencies, thereby enhancing the overall stability of the system. The proposed pull-push configuration markedly improves the slew rate limitation at the gate of the power transistor. Post-layout simulation outcomes, corroborated through a 180-nm CMOS fabrication process, indicate that the proposed LDO regulator maintains stability across a wide range of loading currents, from 0 mA to 100 mA, with a Miller compensation capacitance of only 3.5 pF. The circuit operates with a quiescent current of 143 μA when powered by a 1.5 V single supply. The LDO regulator boasts a dropout voltage of 300 mV, enabling it to deliver up to 100 mA of load current. Simulation results show that the undershoot voltage is only 63.7 mV when the load current jumps from 0 to 100 mA with edge of 100 ns, while employing a 100 pF capacitance load. The recovery time to return to equilibrium post this abrupt change is approximately 0.15 μs. The proposed OCL-LDO regulator exhibits a substantial enhancement in transient response compared to its predecessors, alongside a harmonized balance between line regulation and load regulation performance parameters.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141731789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

The synergistic design of 5 V ESD protection applications using two holding voltage improving methods 利用两种保持电压改进方法协同设计 5 V ESD 保护应用

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-17 DOI: 10.1016/j.mejo.2024.106348

引用次数: 0

A circuit protection method based on replacing minterms with combinatorial circuits 基于用组合电路取代小项的电路保护方法

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-17 DOI: 10.1016/j.mejo.2024.106314

引用次数: 0

Novel superjunction Fin-based NiO/β-Ga2O3 HJFET with additional surface drift region channels for record-high performance 基于鳍片的新型超结 NiO/β-Ga2O3 HJFET，具有额外的表面漂移区通道，可实现创纪录的高性能

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-17 DOI: 10.1016/j.mejo.2024.106325

{"title":"Novel superjunction Fin-based NiO/β-Ga2O3 HJFET with additional surface drift region channels for record-high performance","authors":"","doi":"10.1016/j.mejo.2024.106325","DOIUrl":"10.1016/j.mejo.2024.106325","url":null,"abstract":"<div>—In this paper, a novel superjunction ﬁn-based NiO/β-Ga2O3 heterojunction ﬁeld-effect transistor (SJ Fin-HJFET) is proposed and studied by simulations. Compared with the conventional Ga2O3 SJ FinFET, Ga2O3 SJ Fin-HJFET can generate surface conduction channels instead of depletion zones near the p-n junction interface in the SJ drift region. The additional surface conduction channel significantly improves the specific on-resistance of the SJ Fin-HJFET (from 1.091 mΩ cm2 to 0.397 mΩ cm2, reduced by 63.6 %) and dramatically improves the Baliga figure of merit (BFOM, form 11.75 GW/cm2 to 32.28 GW/cm2) at the same breakdown voltage (3580 V). The effect of different conduction band offset (ΔEC) on the performance of the SJ Fin-HJFET is also investigated. The simulation results show that the on-resistance advantage of the SJ Fin-HJFET applies to a wide range of ΔEC, exhibiting strong applicability and stability. These results indicate that the SJ Fin-HJFET has record-high performance and promising application prospects.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141842770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Short failure localization in advanced package using optoelectronic sampling terahertz time domain reflectometry and deconvolution method 使用光电采样太赫兹时域反射仪和解卷积法定位高级封装中的短故障

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-17 DOI: 10.1016/j.mejo.2024.106310

引用次数: 0

A low-noise multipath operational amplifier with Gm-shared ping-pong and ripple averaging techniques 采用 G 共享乒乓和纹波平均技术的低噪声多路径运算放大器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-17 DOI: 10.1016/j.mejo.2024.106306

引用次数: 0