Microelectronics Journal最新文献_第8页

Thermal analysis of GaN HEMTs using nongray multi-speed phonon lattice Boltzmann method under Joule heating effect 焦耳加热效应下使用非灰色多速声子晶格玻尔兹曼法对氮化镓 HEMT 进行热分析

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-08-11 DOI: 10.1016/j.mejo.2024.106366

Xixin Rao, Yipeng Wu, Kongzhang Huang, Haitao Zhang, Chengdi Xiao

{"title":"Thermal analysis of GaN HEMTs using nongray multi-speed phonon lattice Boltzmann method under Joule heating effect","authors":"Xixin Rao, Yipeng Wu, Kongzhang Huang, Haitao Zhang, Chengdi Xiao","doi":"10.1016/j.mejo.2024.106366","DOIUrl":"10.1016/j.mejo.2024.106366","url":null,"abstract":"<div>Gallium Nitride (GaN) high electron mobility transistors (HEMTs) exhibit superior electrical properties for power and radio frequency applications, but performance is compromised by localized Joule heating, increasing channel temperatures. Precise thermal analysis during design is essential for optimizing device architecture and management strategies. Traditional methods like the Fourier heat diffusion equation (HDE) and the phonon lattice Boltzmann method (PLBM) with the D2Q8 scheme inadequately model phonon ballistic transport at high Knudsen numbers. This study introduces a nongray multi-speed PLBM integrated with the drift-diffusion model to analyze electro-thermal processes in GaN HEMTs. Validated through simulations of thermal conductivities in two-dimensional GaN thin films, the approach examines internal temperature rise in GaN HEMTs under different gate voltages, comparing results with HDE and gray BTE models, and emphasizing the need for non-Fourier effects in thermal analysis. It also evaluates the impact of GaN layer thickness on temperature distribution, providing a robust solution for thermal analysis in GaN HEMTs and other field-effect transistors.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141984846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-throughput true random number generator based on a dual-input oscillation circuit 基于双输入振荡电路的高吞吐量真随机数发生器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-08-11 DOI: 10.1016/j.mejo.2024.106367

Yingchun Lu , Bolin Sun , Enpu Xu , Changlong Cao , Linghui Zhang , Liang Yao

引用次数: 0

High-k2eff AlSc0.095N-based two-dimensional coupled mode resonators with transducer design toward 5G application 基于 AlSc0.095N 的高 k2eff 二维耦合模式谐振器与面向 5G 应用的换能器设计

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-08-09 DOI: 10.1016/j.mejo.2024.106364

Zexin Sun , Shitao Lv , Wenhao Ye , Xinyi Sun , Haiyan Sun , Jicong Zhao

{"title":"High-k2eff AlSc0.095N-based two-dimensional coupled mode resonators with transducer design toward 5G application","authors":"Zexin Sun , Shitao Lv , Wenhao Ye , Xinyi Sun , Haiyan Sun , Jicong Zhao","doi":"10.1016/j.mejo.2024.106364","DOIUrl":"10.1016/j.mejo.2024.106364","url":null,"abstract":"<div>This paper presents the two-dimensional coupled mode resonators (TCMRs) based on 9.5 % scandium-doped aluminum nitride (AlScN) films. We report the design, fabrication, and characterization of 770 nm-thick AlSc0.095N TCMRs, which utilize the e31 and e33 piezoelectric coefficients to jointly excite the coupled mode with high electromechanical coupling coefficient (k2eff). The TCMRs with different electrical boundary conditions (TCMR-I and TCMR-II) are proposed, and the dependence of the resonant mode on the electrode period was studied. The effect of electrode duty factor (DF) on the resonator performance was explored, and both TCMR-Ⅰ and TCMR-II with DF = 0.5 exhibit the maximum k2eff value. Through measured characterization and simulation analysis, the effect of interdigitated transducer (IDT) thickness on resonator performance was studied. In addition, the equivalent electrical parameters of the prepared resonator were extracted using the MBVD equivalent circuit model. The Qs values of TCMR-Ⅰ and TCMR-II fabricated in this paper can reach 1134 and 165, and the k2eff values can reach 3.5 % and 7.86 %, respectively.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141953685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Ohmic contacts to n-type SiC: Influence of Au and Ta intermediate layers 与 n 型碳化硅的欧姆接触：金和钽中间层的影响

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-08-08 DOI: 10.1016/j.mejo.2024.106361

Chanchal , Mohammad Faisal , Robert Laishram , Sharmila , Sonalee Kapoor , Jaya Lohani , D.S. Rawal , Manoj Saxena

{"title":"Ohmic contacts to n-type SiC: Influence of Au and Ta intermediate layers","authors":"Chanchal , Mohammad Faisal , Robert Laishram , Sharmila , Sonalee Kapoor , Jaya Lohani , D.S. Rawal , Manoj Saxena","doi":"10.1016/j.mejo.2024.106361","DOIUrl":"10.1016/j.mejo.2024.106361","url":null,"abstract":"<div>In this study, the optimization of metal-semiconductor contacts to reduce the contact resistance of ohmic contacts on n-type 4H-SiC. The commonly used Ni/Au metal scheme served as a reference. We introduced two novel metal schemes: (i) incorporating a thin interfacial Au layer (2 nm) into Ni/Au, resulting in Au/Ni/Au, and (ii) introducing a thin intermediate barrier layer of Ta (20 nm) into Ni/Au, resulting in Ni/Ta/Au. Rapid thermal annealing (RTA) is performed at different temperatures and durations and the electrical characteristics of the contacts are measured. X-ray diffraction analysis was employed to investigate the intermediate phases formed during annealing. In the Au/Ni/Au metal scheme, the presence of Au at the interface promoted the formation of additional phases of nickel-silicide (Ni3Si and Ni3Si2). Compared to the traditional Ni/Au scheme, the modified metal schemes led to lower surface roughness and reduced contact resistance. Specific contact resistivity values are calculated, 2.2 × 10−5 Ω-cm2 for Ni/Au, 1.37 × 10−5 Ω-cm2 for Au/Ni/Au, and 4.84 × 10−5 Ω-cm2 for Ni/Ta/Au. This research offers valuable insights for the selection of metal schemes in designing ohmic contacts on n-type SiC, with potential applications in various semiconductor device technologies.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141953389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Power-efficient wideband programmable pseudo differential ring oscillator CP-PLL 高能效宽带可编程伪差分环振荡器 CP-PLL

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-08-08 DOI: 10.1016/j.mejo.2024.106365

Bo Liu , He Yang , Xiangjun Wang , Ruizhi Xiang , Jun Wang , Liwen Zhang

引用次数: 0

Machine learning driven global optimisation framework for analog circuit design 机器学习驱动的模拟电路设计全局优化框架

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-08-06 DOI: 10.1016/j.mejo.2024.106362

Ria Rashid , Komala Krishna , Clint Pazhayidam George , Nandakumar Nambath

{"title":"Machine learning driven global optimisation framework for analog circuit design","authors":"Ria Rashid , Komala Krishna , Clint Pazhayidam George , Nandakumar Nambath","doi":"10.1016/j.mejo.2024.106362","DOIUrl":"10.1016/j.mejo.2024.106362","url":null,"abstract":"<div>We propose a machine learning-driven optimisation framework for analog circuit design in this paper. Machine learning based global offline surrogate models, with the circuit design parameters as the input, are built in the design space for the analog circuits under study and are used to guide the optimisation algorithm towards an optimal circuit design, resulting in faster convergence and reduced number of spice simulations. Multi-layer perceptron and random forest regressors are employed to predict the required design specifications of the analog circuit. Multi-layer perceptron classifiers are used to predict the saturation condition of each transistor in the circuit. We validate the proposed framework using three circuit topologies—a bandgap reference, a folded cascode operational amplifier, and a two-stage operational amplifier. The simulation results show better optimum values and lower standard deviations for fitness functions after convergence, with a reduction in spice calls by 56%, 59%, and 83% when compared with standard approaches in the three test cases considered in the study.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141979398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 40 mV cold-start circuit with bootstrap clock booster for thermoelectric energy harvesting 用于热电能量采集的带自举时钟助推器的 40 mV 冷启动电路

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-08-06 DOI: 10.1016/j.mejo.2024.106360

Haizhun Wang , Yinshui Xia , Xiudeng Wang, Zhidong Chen

引用次数: 0

A PVT-robust Gm-R-based residue amplifier with folded positive feedback technique 采用折叠正反馈技术的基于 PVT 的 Gm-R 残差放大器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-08-06 DOI: 10.1016/j.mejo.2024.106352

Haolin Han, Jinwei Zhang, Ruili Ren, Yi Shen, Shubin Liu, Ruixue Ding

引用次数: 0

A demultiplexer-based dual-path switching true random number generator 基于解复用器的双路径切换真随机数发生器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-08-06 DOI: 10.1016/j.mejo.2024.106363

Tianming Ni , Kejie Xu , Hao Wu , Senling Wang , Mu Nie

引用次数: 0

Performance enhancement of 4H-SiC superjunction trench MOSFET with extended high-K dielectric 采用扩展高介电质的 4H-SiC 超结沟槽 MOSFET 的性能提升

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-08-05 DOI: 10.1016/j.mejo.2024.106359

Jiafei Yao , Zhengfei Yang , Yeqin Zhu , Qing Yao , Jing Chen , Kemeng Yang , Man Li , Maolin Zhang , Jun Zhang , Yufeng Guo

{"title":"Performance enhancement of 4H-SiC superjunction trench MOSFET with extended high-K dielectric","authors":"Jiafei Yao , Zhengfei Yang , Yeqin Zhu , Qing Yao , Jing Chen , Kemeng Yang , Man Li , Maolin Zhang , Jun Zhang , Yufeng Guo","doi":"10.1016/j.mejo.2024.106359","DOIUrl":"10.1016/j.mejo.2024.106359","url":null,"abstract":"<div>This paper proposes a 4H-SiC superjunction trench MOSFET with extended high-K dielectric under metal gate (EHK SJ-TMOS). The characteristics of EHK SJ-TMOS include the use of the high-K (HK) dielectric as the gate dielectric and the extension of the HK dielectric as a deep trench into the N-type drift region. The extended HK trench effectively modulates the electric field distribution in the SJ drift region, which improves the breakdown voltage (BV). The introduction of HK dielectric also assists in depleting the SJ drift region, which enables the drift region of EHK SJ-TMOS to use a higher doping concentration, thereby reducing Ron,sp. Furthermore, the application of high-K gate dielectric alleviates the high gate oxide electric field problem in conventional SiC superjunction trench MOSFETs (SiC SJ-TMOS). The simulation results demonstrate that EHK SJ-TMOS exhibits a 59.2 % reduction in Ron,sp, a 2.4 % increase in BV, and a 156.5 % improvement in the FOM (FOM = BV2/Ron,sp) compared to the SiC SJ-TMOS, indicating enhanced performance.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141962710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0