Microelectronics Journal最新文献_第8页

A fully-integrated VCO-based analog-assisted-digital low-dropout regulator with feed-forward PSR enhancement for energy-harvesting wireless sensor node

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106322

Zhenglai Wang , Bo Zhao , Jianming Zhao , Yuxuan Luo

{"title":"A fully-integrated VCO-based analog-assisted-digital low-dropout regulator with feed-forward PSR enhancement for energy-harvesting wireless sensor node","authors":"Zhenglai Wang , Bo Zhao , Jianming Zhao , Yuxuan Luo","doi":"10.1016/j.mejo.2024.106322","DOIUrl":"10.1016/j.mejo.2024.106322","url":null,"abstract":"<div><div>The sensor nodes within wireless sensor networks (WSNs) can harvest energy from the environment to supplement their power needs. The sensor node requires a low-voltage regulator to condition the weak and unstable harvested energy. This paper presents a self-clocked fully-integrated feedforward-biased hybrid low-dropout regulator (FFB-HLDO) with a dual differential VCO (DD-VCO) pair for WSN sensor applications. The proposed HLDO is fully integrated without load capacitor. To enhance the Power Supply Rejection (PSR) performance, an analog feedforward biased (AFFB) technique is proposed to reduce supply ripples. Besides, a distortion module (DM) is proposed to improve the transient response. Implemented in a 65 nm CMOS technology, this capacitor-less and self-clocked HLDO can provide the minimum output of 0.3V and the maximum output of 1.5V from 0.55–1.6V input, and the area is 0.0123 mm<sup>2</sup>. For the maximum load current of 0.26 mA, the peak current efficiency is 98.9%. With a quiescent current of 300 nA, the frequency of 0-dB-PSR is 100 MHz.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106322"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143162265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A sub-6 GHz and millimeter-wave IPD tri-band bandpass filter chip with wide stopband, high roll-off, and enhanced bandwidth

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106527

Yuxin Liu , Yongle Wu , Shuchen Zhen , Yuhao Yang , Weimin Wang , Qinghua Yang

引用次数: 0

A 32-channels analog multiplexer with crosstalk compensation technique in 45 nm CMOS

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106496

Jie Wu, Qiao Meng, Gaojing Li, Sha Li, Shaocong Guo, Yujia Huang

{"title":"A 32-channels analog multiplexer with crosstalk compensation technique in 45 nm CMOS","authors":"Jie Wu, Qiao Meng, Gaojing Li, Sha Li, Shaocong Guo, Yujia Huang","doi":"10.1016/j.mejo.2024.106496","DOIUrl":"10.1016/j.mejo.2024.106496","url":null,"abstract":"<div><div>This paper presents a multiplexer that is capable of modulating 32-channels analog signal, which is a promising approach to simplify transmission system. An 8-channels prototype multiplexer with integral functionality and non-ideal factors is fabricated in 45 nm CMOS with area of 0.59 mm<sup>2</sup>, and verified in a QAM-256 system with 1.2V supply. The proposed multiplexer employs a semi-tree structure to achieve compromise between scale and speed. To relieve adverse effect caused by crosstalk between channels, the auxiliary reset compensation circuit combined with a dedicated timing sequence is utilized. Additionally, the proposed high-speed gate voltage bootstrap switch and high-bandwidth input buffer ensure that the signal remains linear during transmission. In the experimental result, the multiplexer can achieve a pulse width of at least 77ps in 8Gbps code rate, and the root mean square error due to nonlinearity between differential input and output is 1.869 %. The error vector magnitude (EVM) obtained by analyzing output versus input of multiplexer is less than 1.413 %.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106496"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143163322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A cross-scale investigation on transient electrothermal performance for power MOSFETs at device-package level

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2025.106561

Yuxuan Dai , Jiafei Yao , Jing Chen , Maolin Zhang , Yucheng Xu , Qing Yao , Qingyou Qian , Jun Zhang , Kemeng Yang , Yufeng Guo

{"title":"A cross-scale investigation on transient electrothermal performance for power MOSFETs at device-package level","authors":"Yuxuan Dai , Jiafei Yao , Jing Chen , Maolin Zhang , Yucheng Xu , Qing Yao , Qingyou Qian , Jun Zhang , Kemeng Yang , Yufeng Guo","doi":"10.1016/j.mejo.2025.106561","DOIUrl":"10.1016/j.mejo.2025.106561","url":null,"abstract":"<div><div>This article proposes a fully automated cross-scale relaxation scheme for analyzing the temporal electrothermal behavior of power MOSFETs, spanning from the complete micrometer-scale devices to the millimeter-scale packages. The presented scheme integrates the device-level technology computer-aided design (TCAD) simulator Silvaco with the package-level finite element analysis (FEA) simulator ANSYS Icepak, achieving self-consistent electrothermal effects. It reduces data transfer time between the simulators while harnessing their complementary strengths to address complex device structures, package structures, and heat flow environments. Simulation results are then compared with alternative methods, and their distinct features are analyzed in detail. Furthermore, empirical models are derived to characterize electrothermal parameters and extract the thermal time constant. The method's effectiveness is validated using a commercial power MOSFET with TO-220F packaging. The simulations, models, and experiments produced highly satisfactory fits, enabling an effective way for device-package-level co-design and rapid determination of thermal time constant.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106561"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143163324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel dual-band power amplifier with integrated harmonic control based on dual transmission lines

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2025.106552

Jindong Zhang, Cuiping Yu, Hao Li, Yuanan Liu

引用次数: 0

A 4.5-MS/s 12-bit Vcm self-generated SAR ADC in 130-nm CMOS

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106548

Dun Yan , Xin Zhang , Yu Xiao , Xiaoyou Yu , Shaoliang Peng , Songting Li , Kai Tang , Jie Liu

{"title":"A 4.5-MS/s 12-bit Vcm self-generated SAR ADC in 130-nm CMOS","authors":"Dun Yan , Xin Zhang , Yu Xiao , Xiaoyou Yu , Shaoliang Peng , Songting Li , Kai Tang , Jie Liu","doi":"10.1016/j.mejo.2024.106548","DOIUrl":"10.1016/j.mejo.2024.106548","url":null,"abstract":"<div><div>This paper presents a 12-bit, 4.5 MS/s synchronous SAR ADC implemented in SMIC's 130-nm CMOS technology. It features a novel method for internal common-mode (<em>V</em><sub><em>cm</em></sub>) generation via introduces switched-capacitor technique, eliminating the need for external <em>V</em><sub><em>cm</em></sub> generation circuitry and reducing parasitics. To enhance capacitor matching and mitigate mismatch, thermometer encoding is employed for the most significant 6-bit of the ADC. The comparator boasts a dynamic pre-amplifier with switching capacitance tail current for improved signal amplification. The ADC exhibits excellent linearity with DNL of +0.59/−0.57 LSB and INL of +1.02/−1.12 LSB. Occupying a core area of 0.144 mm<sup>2</sup>, it achieves SNDR of 69.63 dB, ENOB of 11.27-bit, SFDR of 78.17 dB, and THD of −76.33 dB. Operating at 3.3 V, it consumes 2.577 mW with FoM<sub>W</sub> of 231.9 fJ/conversion-step. These measurement results confirm the feasibility and effectiveness of the proposed <em>V</em><sub><em>cm</em></sub> self-generation approach, offering fresh insights into <em>V</em><sub><em>cm</em></sub> generation in ADC design, with potential implications for future ADC architectures.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106548"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143162391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A dual-band omnidirectional rectenna for radio-frequency energy harvesting applications

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106533

Jifei Sang , Libo Qian , Xiudeng Wang , Ge Shi

{"title":"A dual-band omnidirectional rectenna for radio-frequency energy harvesting applications","authors":"Jifei Sang , Libo Qian , Xiudeng Wang , Ge Shi","doi":"10.1016/j.mejo.2024.106533","DOIUrl":"10.1016/j.mejo.2024.106533","url":null,"abstract":"<div><div>—This paper proposes a dual-band flexible omni-directional rectenna for radio frequency energy harvesting (RFEH) applications. The rectenna is developed for WLAN/Wi-Fi (2.4 GHz) and 5G (3.5 GHz) bands. First, a dual-band impedance matching network is introduced, and its operating principles are analyzed in detail. The network is applied to design the rectifier, followed by fabrication and measurement of the rectifier operating at 2.4/3.5 GHz. At an input power level of −10 dBm, the overall radio frequency (RF) to direct current (DC) power conversion efficiency (PCE) reaches 27.1 % at 2.4 GHz and 20.0 % at 3.5 GHz. Then, a wideband omnidirectional monopole antenna is realized as the receiving antenna for the designed rectifier. The antenna broadens its operating bandwidth by utilizing a tapered microstrip feed and etching a cross-shaped groove on the ground plane. Measured results indicate that the antenna can capture RF energy omnidirectionally within the bandwidth of 2.2–6 GHz, satisfying the demands of the rectifier. Lastly, the prototype of the rectenna is fabricated and tested by integrating the rectifier and monopole antenna into a low-profile design. The experimental results demonstrate that the proposed rectenna is competitive in terms of PCE, flexibility, and compactness. This indicates its enormous potential for numerous battery-free or low-power applications in the real world.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106533"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143163109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Compact bandpass filter with low insertion loss and high selectivity based on 3D glass-based IPD technology

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106539

Xueyuan Zhang, Yazi Cao, Xiaoyan Yang, Jialong Xin, Gaofeng Wang

{"title":"Compact bandpass filter with low insertion loss and high selectivity based on 3D glass-based IPD technology","authors":"Xueyuan Zhang, Yazi Cao, Xiaoyan Yang, Jialong Xin, Gaofeng Wang","doi":"10.1016/j.mejo.2024.106539","DOIUrl":"10.1016/j.mejo.2024.106539","url":null,"abstract":"<div><div>A compact bandpass filter with low insertion loss and high selectivity is presented using 3D glass-based IPD technology. A modified asymmetric π structure is introduced to generate three poles to achieve wide bandwidth and low insertion loss. In order to achieve better selectivity and higher out-of-band rejection, the introduced modified asymmetric π structure is adopted to generate two controllable transmission zeros on both sides of the passband. Compared to the traditional π structure, the modified π structure does not require the design to be completely symmetrical, thereby providing the filter design greater flexibility. High-Q 3D inductors based on 3D glass-based technology are utilized to achieve lower insertion loss. The proposed bandpass filter, which covers the band of 2.4–2.9 GHz, is fabricated with a compact size of 1.6 mm × 0.8 mm × 0.35 mm. The measured results show that it can achieve an insertion loss less than 1.6 dB and a return loss better than 15 dB in the passband. Its out-of-band rejection is better than 24 dB from DC to 1.89 GHz and from 3.7 GHz to 10 GHz. The simulated and measured results of the proposed BPF are in reasonably good agreement.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106539"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143163162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Exploring the impact of sheet thickness scaling on Nanosheet FET gate electrostatics using k.p based simulations

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106480

Ramandeep Kaur, Nihar R. Mohapatra

引用次数: 0

Analytical modeling of cylindrical Silicon-on-Insulator Schottky Barrier MOSFET and impact of insulator pillar radius on analog/RF and linearity parameters for low power circuit application

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106505

Jitender Kumar , Amit Saxena , S.S. Deswal , Aparna N. Mahajan , R.S. Gupta

{"title":"Analytical modeling of cylindrical Silicon-on-Insulator Schottky Barrier MOSFET and impact of insulator pillar radius on analog/RF and linearity parameters for low power circuit application","authors":"Jitender Kumar , Amit Saxena , S.S. Deswal , Aparna N. Mahajan , R.S. Gupta","doi":"10.1016/j.mejo.2024.106505","DOIUrl":"10.1016/j.mejo.2024.106505","url":null,"abstract":"<div><div>In the current scenario of semiconductor technologies, the researchers are investigating the cylindrical Silicon-on-Insulator Schottky Barrier (SOISB) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) due to its enhanced analog/RF parameters, high I<sub>ON</sub>/I<sub>OFF</sub> ratio and reduced ambipolarity. This study presents an analytical model for the cylindrical SOISB MOSFET, specifically focusing on how to calculate surface potential, threshold voltage, and drain current. Further, the research explores how altering the radius of the concentric SiO<sub>2</sub> insulator pillar impacts the MOSFETs performance in analog/RF circuit applications. The Silvaco 3D device simulator has been used for conducting the numerical simulations for a channel length of 22 nm and a silicon radius of 5 nm. The SiO<sub>2</sub> insulator pillar radius has been varied from 1 nm to 4 nm and its effect on the device characteristics has been investigated. The results show improved changes in analog/RF parameters and linearity, providing valuable insights for advanced semiconductor technologies.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106505"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143163290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0