Microelectronics Journal最新文献

{"title":"Power-efficient SAR ADC with noise-reduction scheme based on kT/C noise cancellation and adaptive tracking averaging","authors":"Anji Huang ,&nbsp;Gefeng Zeng ,&nbsp;Yi Shen ,&nbsp;Angyang Li ,&nbsp;Libo Qian ,&nbsp;Qing Zou ,&nbsp;Zheng Qiu ,&nbsp;Min Wang ,&nbsp;Shubin Liu ,&nbsp;Ruixue Ding ,&nbsp;Yinshui Xia ,&nbsp;Zhangming Zhu","doi":"10.1016/j.mejo.2025.106599","DOIUrl":"10.1016/j.mejo.2025.106599","url":null,"abstract":"<div><div>Conventional successive approximation register (SAR) ADCs encounter a compromise between accuracy and power consumption. This work presents an efficient noise-reduction scheme to mitigate sampling noise and comparator noise. The kT/C noise cancellation technique reduces the kT/C noise and facilitates the reduction of the sampling capacitance to one-sixth of its typical value in conventional architectures. LSB repeating and adaptive tracking averaging(ATA) technique are also employed to decouple the correlation between the energy and the noise in the comparator. Post-simulation results indicate that the signal-to-noise distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of the proposed 14-bit prototype SAR ADC attain values of 84.5 dB and 95.5 dB respectively at a Nyquist input rate and a sampling rate of 1 MS/s. The power consumption is 431.6 <span><math><mi>μ</mi></math></span>W with a 1.8 V power supply, resulting in a “Walden” figure of merit (FoMw) of 35.7 fJ/conv-step and a “Schreier” figure of merit (FoMs) of 173.3 dB in a 0.18-<span><math><mi>μ</mi></math></span>m CMOS process.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106599"},"PeriodicalIF":1.9,"publicationDate":"2025-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143471711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An area-efficient and process-variable insensitive readout circuit for Computing-in-Memory based on NOR flash","authors":"Xiaofeng Gu,&nbsp;Hai Zhou,&nbsp;Yang Qiao,&nbsp;Xiaoyu Zhong,&nbsp;Zhiguo Yu","doi":"10.1016/j.mejo.2025.106598","DOIUrl":"10.1016/j.mejo.2025.106598","url":null,"abstract":"<div><div>Readout circuit is crucial to the performance of a Computing-in-Memory (CIM) macro, as it occupies a significant portion of the macro’s area and power consumption. This paper proposes a readout circuit for NOR flash-based CIM macro to improve area efficiency and adaptability to process variations. It is characterized by (1) a global clamp-based current sensing circuit, (2) an accumulating analog-to-digital converter, and (3) a calibration scheme based on the reference sample-and-hold circuitry. With the proposed readout circuit, the 55-nm CIM macro with a crossbar size of 265 × 256 achieves an energy efficiency of 20.4 TOPS/W and a computational density of 0.29 TOPS/mm<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span> with 8-bit input, 8-bit weights, and 8-bit output precision. Furthermore, the evaluation results of readout circuits using VGG-16 show that the proposed calibration scheme effectively mitigates the degradation of inference accuracy caused by process variations.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106598"},"PeriodicalIF":1.9,"publicationDate":"2025-02-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143487048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Humidity and ring spacing variation tolerant design of a SiC power MOSFET using mirrored floating field rings","authors":"Prashant Singh ,&nbsp;Shreepad Karmalkar ,&nbsp;Akshay K","doi":"10.1016/j.mejo.2025.106611","DOIUrl":"10.1016/j.mejo.2025.106611","url":null,"abstract":"<div><div>Prior designs of the number and spacing of the Floating Field Rings (FFRs) in the edge termination of SiC MOS-FETs have limitations. They neglect the possible degradation of the breakdown voltage, <em>V</em>_<em>BR</em>, due to two reasons: (1) widening, <em>α</em>, of the ring due to lateral straggle of dopants during implant-action, and over-etching of the window during the prior lithography step; (2) presence of a negative SiC/SiO₂ interface charge, <em>Q</em>_<em>H</em>, over a part or whole of the edge termination length due to migration of aluminates formed from reaction of the gate metal with humidity in the environment. We propose an improved algorithm to design a FFR structure considering <em>α</em>. Further, we show that by extending this structure by its mirrored version, we get what we call a Mirrored FFR (MFFR) structure, which is tolerant to <em>Q</em>_<em>H</em> as well as <em>α</em>. The concept is illustrated using well calibrated TCAD simulations of a 600 V SiC MOSFET with α = 0.3 μm and <em>Q</em>_<em>H</em> = − 3 × 10¹² cm⁻²; the <em>V</em>_<em>BR</em> with prior FFR designs degraded by up to 48 % while that with MFFR design by just 16 %. Thus, MFFR structure yields a device with the least overhead factor of <em>V</em>_<em>BR</em>, that in turn allows realization of a lower specific on-resistance.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106611"},"PeriodicalIF":1.9,"publicationDate":"2025-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143509043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Bandwidth optimization for GaN HEMT terahertz detectors using the advanced SPICE model","authors":"Chaoyu Zhang,&nbsp;Xiaolong Hu","doi":"10.1016/j.mejo.2025.106600","DOIUrl":"10.1016/j.mejo.2025.106600","url":null,"abstract":"<div><div>This paper presents a solution to address the problems for AlGaN/GaN HEMT terahertz detectors. An ASM GaN HEMT model is first developed and validated for the GaN HEMT terahertz detectors using ICCAP simulation. Then, a common-source amplification mode GaN HEMT amplifier with a large impedance is selected for integration with the detector, which offers a higher input impedance and thereby facilitates a better impedance match with the detector. An optimal bandwidth of 212.1 MHz was obtained when the gate voltage of the IF amplifier is at −1.8 V. Finally, the circuit matching is optimized between the GaN HEMT detector and the IF amplifier, and the bandwidth of the integrated chip reaches 626.0 MHz, representing an increase of about 195 % compared to the configuration without circuit matching.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106600"},"PeriodicalIF":1.9,"publicationDate":"2025-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143509027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 16-bit 20KSPS SAR ADC with digital background calibration in 0.18 μm CMOS","authors":"Xiaoyuan Miao,&nbsp;Yuhua Liang","doi":"10.1016/j.mejo.2025.106610","DOIUrl":"10.1016/j.mejo.2025.106610","url":null,"abstract":"<div><div>For intelligent Internet of Things applications (IoT) in sustainable agriculture and food industries, after sensors gather environmental data, the quantization process demands low bandwidth and high-precision ADCs. This article presents a 16-bit successive-approximation register (SAR) analog-to-digital converters (ADCs) with a background digital calibration based on Dither and LMS. The proposed SAR ADC is demonstrated through sequential modeling in MATLAB, pre-layout, and post-layout. Designed in a 0.18 μm process, the post-layout simulation results show that it achieves a peak SNDR of 90.1 dB, and a peak SFDR of 106.7 dB with a 10 kHz bandwidth. The power consumption of this SAR ADC is 176.8 μW under a 5V supply. The Schreier Figure-of Merit (FoM_SNDR) is 167.6 dB. The ADC suits low-speed, high-precision IoT systems in sustainable agriculture and food industries.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106610"},"PeriodicalIF":1.9,"publicationDate":"2025-02-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143453849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability analysis of PoP stacked solder joints under thermal cycling load based on the optimal equivalent model","authors":"Chao Gao ,&nbsp;Chunyue Huang ,&nbsp;Ying Liang ,&nbsp;Gui Wang ,&nbsp;Yongling Chen","doi":"10.1016/j.mejo.2025.106596","DOIUrl":"10.1016/j.mejo.2025.106596","url":null,"abstract":"<div><div>An optimal equivalent model for PoP-stacked solder joints is developed based on the nonlinear load-deformation response. The thermal stress distribution of solder joints in PoP assembly arrays subjected to thermal cycling loads is simulated and analyzed. The thermal fatigue failure modes of critical solder joints in the array are discussed, and the thermal fatigue life of these joints is calculated. Furthermore, the influence of structural parameters on solder joint thermal stress is elucidated. The results indicate that the incorporation of the optimal equivalent model not only improves the efficiency of simulation analysis but also enhances the accuracy of solder joint thermal stress prediction. The solder joints in the lower array of the PoP assembly experience higher thermal stress compared to those in the upper array. Solder joints at the corners of the array exhibit higher thermal stress and are identified as critical components. Cracks initially nucleate at the interface between the solder joint and the copper pad, propagating along the interface and eventually appearing within the solder joint. The thermal fatigue life of critical solder joints in the upper array is 3–4 times longer than that of the critical solder joints in the lower array. The ranking of the influence of specific structural parameters on solder joint thermal stress is as follows: solder joint height &gt; solder joint diameter &gt; PCB thickness &gt; substrate thickness. Thermal stress in solder joints exhibits a negative correlation with solder joint height and diameter, and a positive correlation with PCB and substrate thickness.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106596"},"PeriodicalIF":1.9,"publicationDate":"2025-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143444305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A broadband GaAs receiver MMIC for W-band applications","authors":"Zhenbei Li,&nbsp;Huanhuan Guan,&nbsp;Nan Guo,&nbsp;Jian Zhang,&nbsp;Qiuze Yu","doi":"10.1016/j.mejo.2025.106590","DOIUrl":"10.1016/j.mejo.2025.106590","url":null,"abstract":"<div><div>A broadband, multifunctional W-band receiver MMIC (Monolithic Microwave Integrated Circuit) is presented, designed using 0.1-<span><math><mi>μ</mi></math></span>m GaAs pHEMT (pseudomorphic high-electron-mobility transistor) technology from WIN Semiconductors. This MMIC integrates a sextupler, a quadrature resistive mixer, and a low-noise amplifier (LNA), with the sextupler and LNA individually fabricated and tested to optimize performance. Several technologies were employed to enhance the performance of the receiver MMIC. First, a parallel-line coupler, acting as a high-pass filter, reduces lower-order harmonics in the LO chain. Second, radial stubs are applied to chock DC paths in the LO chain for broadband operation. Third, an on-chip LC low-pass filter is incorporated in the IQ mixer to achieve a broad intermediate frequency (IF) bandwidth while minimizing LO signal leakage to the IF port. Measurement results demonstrate a conversion gain of 7–9.5 dB and a noise figure of 5.1–8 dB across an 85–115 GHz frequency range. Compared to other W-band receivers utilizing III-V semiconductor technologies, this GaAs-based receiver MMIC offers a broader operating bandwidth and a competitive noise figure, all within a compact size of <span><math><mrow><mn>2</mn><mo>.</mo><mn>3</mn><mo>×</mo><mn>2</mn><mspace></mspace><msup><mrow><mi>mm</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span>. These attributes make it highly suitable for various W-band applications, including wireless backhaul, radiometry, and millimeter-wave imaging.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106590"},"PeriodicalIF":1.9,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143421501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Narrowband ladder-type MEMS filter based on high-Q thin-film piezoelectric-on-silicon MEMS resonators","authors":"Kewen Zhu ,&nbsp;Yuhao Xiao ,&nbsp;Wen Chen ,&nbsp;Guoqiang Wu","doi":"10.1016/j.mejo.2025.106588","DOIUrl":"10.1016/j.mejo.2025.106588","url":null,"abstract":"<div><div>This article reports a narrowband ladder-type microelectromechanical system (MEMS) filter based on thin-film piezoelectric-on-silicon (TPoS) MEMS resonators with high quality factors (<span><math><mrow><mi>Q</mi><mi>s</mi></mrow></math></span>). The reported second-order ladder-type MEMS filter consists of three single-port TPoS MEMS resonators. Dependencies of the resonator’s <span><math><mi>Q</mi></math></span> and effective electromechanical coupling factor (<span><math><msubsup><mrow><mi>k</mi></mrow><mrow><mi>e</mi><mi>f</mi><mi>f</mi></mrow><mrow><mn>2</mn></mrow></msubsup></math></span>), as well as the filter’s bandwidth on the device thickness of the TPoS MEMS resonators are investigated using finite element method (FEM) analysis. The mechanical <span><math><mi>Q</mi></math></span> of the resonator increases while its <span><math><msubsup><mrow><mi>k</mi></mrow><mrow><mi>e</mi><mi>f</mi><mi>f</mi></mrow><mrow><mn>2</mn></mrow></msubsup></math></span> decreases as the thickness of the silicon device layer become thicker from <span><math><mrow><mn>20</mn><mspace></mspace><mi>μ</mi><mi>m</mi></mrow></math></span> to <span><math><mrow><mn>60</mn><mspace></mspace><mi>μ</mi><mi>m</mi></mrow></math></span>, resulting in a lower insertion loss and narrower bandwidth for the designed filter. Measurement results illustrate that the fabricated TPoS resonator with silicon device layer of <span><math><mrow><mn>60</mn><mspace></mspace><mi>μ</mi><mi>m</mi></mrow></math></span> achieves a high <span><math><mi>Q</mi></math></span> of 50258 and <span><math><msubsup><mrow><mi>k</mi></mrow><mrow><mi>e</mi><mi>f</mi><mi>f</mi></mrow><mrow><mn>2</mn></mrow></msubsup></math></span> of 0.094% at its resonant frequency of 25.9 MHz, which agree well with the FEM simulated values. Thanks to the high <span><math><mi>Q</mi></math></span> and low <span><math><msubsup><mrow><mi>k</mi></mrow><mrow><mi>e</mi><mi>f</mi><mi>f</mi></mrow><mrow><mn>2</mn></mrow></msubsup></math></span> of the TPoS MEMS resonator, the reported ladder-type MEMS filter achieves a narrow percent bandwidth of 0.059%, a low insertion loss of 0.71 dB, and a 20-dB shape factor of 1.33 under proper termination impedance. It provides a promising way for achieving narrowband MEMS filters for channel selection at radio frequency in wireless communications.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"157 ","pages":"Article 106588"},"PeriodicalIF":1.9,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143387116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 112 dB SFDR 16-bit 1MS/s SAR ADC with an improved and robust analog self-calibration","authors":"Zhaojiang Li ,&nbsp;Wei Zhang ,&nbsp;Suming Chen ,&nbsp;Xizhu Peng ,&nbsp;He Tang","doi":"10.1016/j.mejo.2025.106587","DOIUrl":"10.1016/j.mejo.2025.106587","url":null,"abstract":"<div><div>This paper introduces a highly linear 16-bit successive approximation register (SAR) ADC, featuring an improved and robust analog voltage calibration method. The proposed method precisely measures binary capacitor mismatch and redundant capacitor mismatch, enabling accurate compensation of mismatch error during normal operation. Both theoretical analysis and measurement results confirm that the proposed method can significantly improve ADC linearity and spectrum purity. Remarkably, the additional calibration capacitive digital-to-analog converter (CDAC) occupies only 5% of total CDAC area. The design, implemented in a 180-nm CMOS process, achieves an average spuriousfree dynamic range (SFDR) of 112 dB without employing any dynamic element matching (DEM) techniques and a signal-to-noise and distortion ratio (SNDR) of 92.6 dB. This prototype operating 3.3V power supply and 1MS/s sampling rate consumes 4.82 mW and achieves a figure of merit (FOM)s of 172.7 dB.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106587"},"PeriodicalIF":1.9,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143421502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An 85.6-dB SNDR 1.5 MHz-BW NS-pipelined SAR ADC employing the gain-error-shaping technique to enhance the ADC linearity","authors":"Wenjie Liang ,&nbsp;Dazheng Chen","doi":"10.1016/j.mejo.2025.106593","DOIUrl":"10.1016/j.mejo.2025.106593","url":null,"abstract":"<div><div>This paper presents a noise-shaping (NS) pipelined SAR ADC. For a pipelined-SAR ADC, Gain-error-shaping (GES) techniques executing its function in the digital domain can calibrate and correct amplifier gains, reducing nonlinearity errors introduced by amplifiers and thereby improving the ADC performance. Thanks to the highly digitized structure of SAR ADC, NS-pipelined SAR ADC based on the GES is a promising research direction.</div><div>In a 0.18 μm CMOS process, the proposed ADC achieves a SNDR of 82.57 dB, with the signal bandwidth and the sampling rate being 1.5 MHz and 25 MHz respectively. It consumes 3.37 mW in total at a 1.8-V supply, resulting in a SNDR-based Schreier figure-of-merit (FoMs) of 179.1 dB. The chip area occupied by the ADC core is 1200μm × 800 μm.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"157 ","pages":"Article 106593"},"PeriodicalIF":1.9,"publicationDate":"2025-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143378430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}