Microelectronics Journal最新文献_第8页

Three-dimensional design of SOI LDMOS with high-k film trench and L-shaped gate

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-01-17 DOI: 10.1016/j.mejo.2025.106571

Yue Hu , Tianci Wang , Changmiao Wu , Jing Wang , Yuhua Cheng , Wen-sheng Zhao , Gaofeng Wang

{"title":"Three-dimensional design of SOI LDMOS with high-k film trench and L-shaped gate","authors":"Yue Hu , Tianci Wang , Changmiao Wu , Jing Wang , Yuhua Cheng , Wen-sheng Zhao , Gaofeng Wang","doi":"10.1016/j.mejo.2025.106571","DOIUrl":"10.1016/j.mejo.2025.106571","url":null,"abstract":"<div><div>Based on silicon-on-insulator (SOI) technology, a lateral double-diffused metal-oxide-semiconductor (LDMOS) with high-k film trench (HKT) and L-shaped gate (LG) is proposed in this work. The HK film surrounding the oxide trench can adjust the electric flux flow and the trench/drift interface electric field distribution, which improves both of breakdown voltage (<em>BV</em>) and specific on-resistance (<em>R</em><sub><em>on,sp</em></sub>). Moreover, the LG can modulate the three-dimensional (3-D) surface electric field distribution in the xoz-plane, which prevents the premature breakdown at gate end for the device. In the xoz-plane, the LG dramatically enlarges the current channel width. Correspondingly, the drain needs to expand the area in top view, which can provide sufficient conductive path to match the widened current channel. In a consequence, <em>R</em><sub><em>on,sp</em></sub> significantly decreases. Therefore, <em>BV</em> and <em>R</em><sub><em>on,sp</em></sub> are both effectively improved for the proposed device. The 3-D simulation results show that in comparison with the conventional HKT SOI LDMOS (<em>BV</em> ∼ 255 V, <em>R</em><sub><em>on,sp</em></sub> ∼ 8.72 mΩ∙cm<sup>2</sup>), <em>BV</em> (287 V) is increased by 11.3 % while <em>R</em><sub><em>on,sp</em></sub> (5.37 mΩ∙cm<sup>2</sup>) is reduced by 38 % for the proposed structure, which results in a sufficiently high Figure-of-Merit (<em>FOM</em>, = <em>BV</em><sup><em>2</em></sup><em>/R</em><sub><em>on</em></sub> = 15.3 MW/cm<sup>2</sup>). In addition, the device performance characteristics (e.g. temperature and transconductance) are also discussed in this work.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"157 ","pages":"Article 106571"},"PeriodicalIF":1.9,"publicationDate":"2025-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143141285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of lightweight on-chip one-dimensional convolutional neural network accelerators for edge-end chips

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-01-16 DOI: 10.1016/j.mejo.2025.106570

Haotian Yu , Daibo Zhang , Yaguang Yang , Silong Chen , Zhiqiang Li

{"title":"Design of lightweight on-chip one-dimensional convolutional neural network accelerators for edge-end chips","authors":"Haotian Yu , Daibo Zhang , Yaguang Yang , Silong Chen , Zhiqiang Li","doi":"10.1016/j.mejo.2025.106570","DOIUrl":"10.1016/j.mejo.2025.106570","url":null,"abstract":"<div><div>One-dimensional convolutional neural networks (1D-CNNs) play a crucial role in edge computing applications. To address the challenges of deploying 1D-CNNs on edge devices, this paper proposes a lightweight on-chip 1D-CNN accelerator and its corresponding compilation and deployment process for edge-end chips. The proposed accelerator architecture features an innovative two-stage storage structure, a configurable multiplier-adder tree array, and a comparator array, with an integrated CORDIC core to enhance support for various 1D-CNN architectures. The compilation and deployment process supports operator conversion and fusion, increasing circuit utilization and reducing memory access demands. The accelerator was synthesized using the Global Foundries 22 nm process, achieving a peak throughput of 5.8 GOP/s and a power efficiency of 823.4 GOP/s/W at 200 MHz with an area of 0.056 mm<sup>2</sup>. Comparative testing showed that the proposed design's average computation delay and energy efficiency are 0.520 and 0.145 times that of the ARM Cortex-M7, respectively, demonstrating the proposed accelerator's superior performance and energy efficiency.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"157 ","pages":"Article 106570"},"PeriodicalIF":1.9,"publicationDate":"2025-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143097066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low-power 12T TFET-MOSFET hybrid SRAM bitcell and hybrid 8T SRAM array based on multiplexing strategy

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-01-16 DOI: 10.1016/j.mejo.2025.106569

Wei Hu , Qizhong Zhang , Chenghu Dai , Chunyu Peng , Wenjuan Lu , Xiulong Wu

{"title":"Low-power 12T TFET-MOSFET hybrid SRAM bitcell and hybrid 8T SRAM array based on multiplexing strategy","authors":"Wei Hu , Qizhong Zhang , Chenghu Dai , Chunyu Peng , Wenjuan Lu , Xiulong Wu","doi":"10.1016/j.mejo.2025.106569","DOIUrl":"10.1016/j.mejo.2025.106569","url":null,"abstract":"<div><div>Due to the limitation of MOSFET subthreshold swing, traditional MOSFET-based static random-access memory (SRAM) circuits are difficult to meet the design requirements of low-power integrated circuits. To address these issues, we proposed a half-select disturb-free 12T TFET-MOSFET hybrid SRAM bitcell. It can avoid the forward p-i-n current and effectively mitigate the effect of current degradation, which greatly reduces the static power consumption of the circuit and improves the performance of SRAM. Specifically, compared to 12T, the write delay of the hybrid bitcell decreased by approximately 13.994 % at 0.6 V. Meanwhile, a TFET-MOSFET hybrid 8T SRAM array is proposed by a multiplexing strategy to reduce the area consumption. The proposed <span><math><mrow><mn>4</mn><mo>×</mo><mn>4</mn></mrow></math></span> hybrid SRAM array is comparable to the 12T bitcell in terms of static noise margin (SNM), read/write speed, and static power consumption. These results indicate that the proposed TFET-MOSFET hybrid 8T SRAM array is a good choice for applications that require low power consumption and high stability.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"157 ","pages":"Article 106569"},"PeriodicalIF":1.9,"publicationDate":"2025-01-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143097065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A quad-core wideband Colpitts VCO with 28.2 % bandwidth and −122 dBc/Hz phase noise at 1 MHz offset

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-01-16 DOI: 10.1016/j.mejo.2025.106564

Guoan Wu, Shihao Qi, Qinghua Tang, Wenguang Li, Lamin Zhan

引用次数: 0

Compact switchable microstrip lowpass filter using cross-shaped resonator with sextuple states

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-01-15 DOI: 10.1016/j.mejo.2025.106565

Xiaohan Wan , Guoxin Xu , Zhengzhen Jin , Yifan Wang , Jingru Li , Jintao Deng , Yang Xiong , Yahui Tian , Dan Li , Litian Wang

引用次数: 0

A 12 bit 250 MS/s SAR ADC using level shifted pseudo bottom plates sampling for high conversion rate and wide input amplitude

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-01-13 DOI: 10.1016/j.mejo.2025.106558

Chao Zhao , Hao Zhang , Jie Shao , Can Shi , Dongyang Han , Chengyu Pan , Xusheng Tang

{"title":"A 12 bit 250 MS/s SAR ADC using level shifted pseudo bottom plates sampling for high conversion rate and wide input amplitude","authors":"Chao Zhao , Hao Zhang , Jie Shao , Can Shi , Dongyang Han , Chengyu Pan , Xusheng Tang","doi":"10.1016/j.mejo.2025.106558","DOIUrl":"10.1016/j.mejo.2025.106558","url":null,"abstract":"<div><div>This paper describes a 12 bit 250 Ms/s time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC). A novel level shifted pseudo bottom plates sampling (LSPBS) method is proposed. In contrast to conventional top plates sampling methods, LSPBS effectively mitigates clock feedthrough and charge injection while sustaining a high sampling rate, thereby enhancing the signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) of the ADC. And LSPBS can realize level shift of signals with wide input range, breaking the trade-off between transistor breakdown voltage and signal input range. A metastable elimination comparator is proposed to avoid the problem of ADC circuit failure due to metastable state. In addition, a wide-range DC-coupled buffer is proposed to improve the input range of the SAR ADC and enhance the SNR and linearity. The proposed SAR ADC was implemented using a 28-nm CMOS technology. The capacitance calibration is performed through DEM, without any digital calibration involved. At Nyquist input frequency and a 250 MS/s sampling rate, a SNDR of 59.27 dB and a SFDR of 74.61 dB are achieved, respectively. The core occupies <span><math><mrow><mn>780</mn><mspace></mspace><mi>μ</mi><mi>m</mi></mrow></math></span> <span><math><mo>×</mo></math></span> <span><math><mrow><mn>222</mn><mspace></mspace><mi>μ</mi><mi>m</mi></mrow></math></span>, and consumes a total power of 4.89 mW.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"157 ","pages":"Article 106558"},"PeriodicalIF":1.9,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143097070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Forward and reverse artificial neural network for performance prediction and structural design of bonding wire-based active RF circuit

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-01-13 DOI: 10.1016/j.mejo.2025.106566

Lei Wu

{"title":"Forward and reverse artificial neural network for performance prediction and structural design of bonding wire-based active RF circuit","authors":"Lei Wu","doi":"10.1016/j.mejo.2025.106566","DOIUrl":"10.1016/j.mejo.2025.106566","url":null,"abstract":"<div><div>Accurate optimization and design of active RF circuit play a vital role in attaining high-performance wireless communication systems. Nevertheless, traditional electromagnetic simulation software-based methods still suffer from an unsatisfactory precision rate (<em>P</em>) because of numerous simplifications and assumptions as well as nonlinear effects of active RF chip. Herein, to realize accurate prediction and design of bonding wire-based active RF circuit, a novel approach that utilized measured S-parameters as the dataset and employed forward and reverse artificial neural network (ANN) was proposed, respectively. The feasibility of this approach was verified by taking the low noise amplifier circuit as an example. The phenomenon that circuit performance strongly depends on structural parameters of bonding wires has been revealed and analyzed. Furthermore, the percent bias (PBIAS) of constructed forward and reverse ANN were calculated as 2.3 % and 2.5 %, respectively, demonstrating a high <em>P</em>. Therefore, the proposed approach provides an effective way for accurate optimization and design of active RF circuit.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"157 ","pages":"Article 106566"},"PeriodicalIF":1.9,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143141284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and performance optimization of a stackable Si1-xGex nanosheet gate-controlled thyristor (GCT) DRAM

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-01-13 DOI: 10.1016/j.mejo.2025.106562

Hao He , Lijun Xu , Zhiqiang Li , He Cao , Jianyun Liu , Zeyu Sun , Qinzhi Xu , Zhenhua Wu

{"title":"Design and performance optimization of a stackable Si1-xGex nanosheet gate-controlled thyristor (GCT) DRAM","authors":"Hao He , Lijun Xu , Zhiqiang Li , He Cao , Jianyun Liu , Zeyu Sun , Qinzhi Xu , Zhenhua Wu","doi":"10.1016/j.mejo.2025.106562","DOIUrl":"10.1016/j.mejo.2025.106562","url":null,"abstract":"<div><div>In this study, we propose a novel stackable Si<sub>1−x</sub>Ge<sub>x</sub> nanosheet gate-controlled thyristor (GCT) 1T0C DRAM design, utilizing thyristor-based positive feedback. This design eliminates the need for a separate capacitor, addressing key scalability and power challenges in conventional 1T1C DRAM. Through Technology Computer-Aided Design (TCAD) simulations, we demonstrate that the Si<sub>0.9</sub>Ge<sub>0.1</sub> nanosheets GCT DRAM achieves an on-state current of 2.3 × 10<sup>−4</sup> A, with a voltage hysteresis of over 1.8 V. Furthermore, an extensive material and geometric optimization analysis was conducted, revealing that the GCT device channels can be effectively scaled down to 10 nm. The Si<sub>0.8</sub>Ge<sub>0.2</sub> nanosheet GCT DRAM exhibits a hysteresis memory window exceeding 1.5 V, an exceptionally high on/off current ratio of 10<sup>9</sup>, and a sensing current window of 216 μA. Additionally, the Si<sub>0.57</sub>Ge<sub>0.43</sub> nanosheet GCT DRAM can reduce the positive feedback voltage (V<sub>fb</sub>) to below 0.8 V. This advancement significantly reduces the operating power consumption of the device, making it suitable for next-generation, energy-efficient DRAM applications.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"157 ","pages":"Article 106562"},"PeriodicalIF":1.9,"publicationDate":"2025-01-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143097063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Implication logic synthesis and optimization methods for memristor-based logic circuits

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-01-11 DOI: 10.1016/j.mejo.2025.106553

Tingting Liu, Zhufei Chu

引用次数: 0

An enhanced interlocked feedback structure-based dual-node upset resilient latch

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-01-10 DOI: 10.1016/j.mejo.2025.106555

Na Bai , Zhiwei Liu , Xiaoqing Wen , Yaohua Xu , Yi Wang , Jian Chen , Wenhao Zhu

{"title":"An enhanced interlocked feedback structure-based dual-node upset resilient latch","authors":"Na Bai , Zhiwei Liu , Xiaoqing Wen , Yaohua Xu , Yi Wang , Jian Chen , Wenhao Zhu","doi":"10.1016/j.mejo.2025.106555","DOIUrl":"10.1016/j.mejo.2025.106555","url":null,"abstract":"<div><div>As the integrated circuit technology continues to scale down, the design of Double Node Upset (DNU) resilient latches has become a critical challenge in radiation-hardened design. Traditional designs of resilient latches are primarily based on the Dual Interlocked Storage Cell (DICE) and novel feedback mechanisms. However, these conventional approaches often suffer from significant limitations, such as instability or errors in logic states due to charge sharing during latching, or trade-offs among power consumption, delay, and area. To overcome these challenges, this paper proposes a DNU-resilient latch based on an enhanced interlocked feedback structure. The proposed ISR latch leverages its interlocked feedback mechanism to achieve self-recovery for the maximum number of double-node upset pairs. Simulation results based on the SMIC 28 nm process model demonstrate that the proposed latch can achieve self-recovery under any double-node disturbance. Compared to existing advanced DNU-resilient latches, the proposed design shows superior performance and power efficiency, achieving an average reduction of 81.67% in PDAP.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"157 ","pages":"Article 106555"},"PeriodicalIF":1.9,"publicationDate":"2025-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143097064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0