Microelectronics Journal最新文献_第8页

A 107.5-dB dynamic range 402-μW event-driven dynamic zoom ADC with voice activity detection function for audio applications 107.5 db动态范围402 μ w事件驱动动态变焦ADC，具有语音活动检测功能，适用于音频应用

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-19 DOI: 10.1016/j.mejo.2025.106654

Zhiming Li , Lei Dong , Quan Sun , Yang Chen , Yuming Li , Jie Zhang , Huanhuan Qi , Xiaofei Wang , Hong Zhang

{"title":"A 107.5-dB dynamic range 402-μW event-driven dynamic zoom ADC with voice activity detection function for audio applications","authors":"Zhiming Li , Lei Dong , Quan Sun , Yang Chen , Yuming Li , Jie Zhang , Huanhuan Qi , Xiaofei Wang , Hong Zhang","doi":"10.1016/j.mejo.2025.106654","DOIUrl":"10.1016/j.mejo.2025.106654","url":null,"abstract":"<div><div>This paper presents a dynamic zoom analog-to-digital converter (ADC) for audio applications, which combines a 5-bit coarse event-driven (ED) ADC (also called level-crossing ADC) and a 3rd-order, single-bit discrete-time ΔΣ modulator (ΔΣM). With 2 low-power continuous-time (CT) comparators and a corresponding digital circuit operating only at the event that the input signal crosses the reference levels, the coarse ED ADC consumes much less power than those coarse SAR ADCs operating under the sampling frequency (Fs) in the conventional dynamic zoom ADC schemes, because the ED scheme operates with much less activity and shows higher adaptivity to real acoustic signal applications. Moreover, the ED ADC output can be utilized to generate a voice activity detection (VAD) signal, which provides a simple on-device audio computing function for the analog front-ends in audio applications. A cascoded floating-inverter-amplifier (FIA) based integrator is employed in the fine ΔΣM to reduce power consumption further. Fabricated in a 0.18-μm CMOS process, the prototype ADC chip achieves 102.1-dB peak signal-to-noise ratio (SNR), 103.1-dB peak signal-to-noise-and-distortion ratio (SNDR), and 107.5-dB dynamic range (DR) for a 24-kHz bandwidth and 6.144-MHz Fs, while consuming only 402 μW under the 1.8-V power supply, resulting in a Schreier Figure-of-Merit (FoMs) of 185.3 dB.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106654"},"PeriodicalIF":1.9,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143685621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Compact HRS IPD N77 bandpass filter based on tapered spiral inductors and innovative source-load coupling 紧凑型HRS IPD N77带通滤波器基于锥形螺旋电感和创新的源负载耦合

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-19 DOI: 10.1016/j.mejo.2025.106653

Yuhan Cao, Bukun Xu, Bo Yuan, Gaofeng Wang

引用次数: 0

A PVT-Insensitive instrumentation amplifier with 17.95 mHz high-pass corner based on a PSSP hybrid feedback resistor 基于PSSP混合反馈电阻的17.95 mHz高通角pvt不敏感仪表放大器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-18 DOI: 10.1016/j.mejo.2025.106640

Hao Xu, Shilong Chen, Lu Liu, Guangyin Shi, Tianke Li, Zhiqiang Li, Jun Zhang, Haiying Zhang

{"title":"A PVT-Insensitive instrumentation amplifier with 17.95 mHz high-pass corner based on a PSSP hybrid feedback resistor","authors":"Hao Xu, Shilong Chen, Lu Liu, Guangyin Shi, Tianke Li, Zhiqiang Li, Jun Zhang, Haiying Zhang","doi":"10.1016/j.mejo.2025.106640","DOIUrl":"10.1016/j.mejo.2025.106640","url":null,"abstract":"<div><div>This work presents a capacitively coupled instrumentation amplifier (IA) for applications in the field of physiological signals, and the proposed hybrid resistor realizes its feedback resistance. It allows the capacitively coupled IA to achieve Tera-ohm (T<span><math><mi>Ω</mi></math></span>) feedback resistance and be robust to process, voltage, and temperature (PVT) variations. This hybrid feedback resistor and feedback capacitor of the capacitively coupled IA form a low-pass filter to filter out undesired spike signals. The capacitively coupled IA was implemented in a 130 nm standard CMOS process. The simulation results show that the proposed capacitively coupled IA can realize a high-pass corner of 17.95 mHz and a gain of 36.69 dB. The difference between the maximum and minimum values of the high-pass corner of the capacitively coupled IA under different PVT conditions is only 0.014 Hz. The maximum value of the absolute value of its high-pass corner change rate is 0.30. The proposed capacitively coupled IA can realize a 72.6 dB signal-to-noise and distortion ratio (SNDR).</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106640"},"PeriodicalIF":1.9,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143686092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 257-nA quiescent current 200-mA load low-dropout regulator with reference sampling technique and loop reconfigurable technique 采用参考采样技术和回路可重构技术的257-nA静态电流200-mA负载低压差稳压器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-17 DOI: 10.1016/j.mejo.2025.106648

Shangzheng Yang, Kefan Qin, Xiang Yan, Haitao Cui, Jianwei Zhao, Wei Ma, Weibo Hu, Member, IEEE

{"title":"A 257-nA quiescent current 200-mA load low-dropout regulator with reference sampling technique and loop reconfigurable technique","authors":"Shangzheng Yang, Kefan Qin, Xiang Yan, Haitao Cui, Jianwei Zhao, Wei Ma, Weibo Hu, Member, IEEE","doi":"10.1016/j.mejo.2025.106648","DOIUrl":"10.1016/j.mejo.2025.106648","url":null,"abstract":"<div><div>This paper proposes an ultra-low quiescent current low-dropout regulator (LDO) for Internet-of-Things and portable devices. To reduce power consumption in the reference, the conventional continuous-on reference is replaced by intermittent-on reference, and using switching capacitors to store reference voltage, which called reference sampling technique (RST). Meanwhile, to decrease the quiescent current in LDO main loop, the loop reconfigurable technique (LRT) is implemented. When the LDO with no load, the main loop is two-stage structure with small power transistor, which results in low quiescent current. When a heavy load is added, the main loop is changed into a three-stage structure with large power transistor. A prototype chip is fabricated in 0.35 μm CMOS process, occupying 0.6 mm<sup>2</sup> area and consumes 257 nA quiescent current. Furthermore, owing to the transient enhance circuit, when the load current jumps from 0 mA to 200 mA within 1 μS, the output settling time is about 10 μS, with an undershoot voltage of 160 mV.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106648"},"PeriodicalIF":1.9,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143705555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

X-parameters modeling based on LSTM and CG-BPNN for transistor 基于LSTM和CG-BPNN的晶体管x参数建模

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-17 DOI: 10.1016/j.mejo.2025.106646

Shu-yue Yang , Qian Lin , Hai-feng Wu

引用次数: 0

A double-modules interlocking triple-node upset-tolerant latch design 双模块联锁三节点容错锁存器设计

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-17 DOI: 10.1016/j.mejo.2025.106647

Shiyu Zhao, Qiang Zhao, Licai Hao, Hao Wang, Lang Tian, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Xiulong Wu

{"title":"A double-modules interlocking triple-node upset-tolerant latch design","authors":"Shiyu Zhao, Qiang Zhao, Licai Hao, Hao Wang, Lang Tian, Chunyu Peng, Wenjuan Lu, Zhiting Lin, Xiulong Wu","doi":"10.1016/j.mejo.2025.106647","DOIUrl":"10.1016/j.mejo.2025.106647","url":null,"abstract":"<div><div>In the design of nanoscale latches, multi-node upset (MNU) caused by charge-sharing effects are a major reliability issue. To effectively tolerate MNU under single event effects (SEE), this paper proposes a double-modules interlocking triple-node upset (DMITNU) tolerant latch design. Based on the radiation upset mechanism, utilizing polarity hardened and source isolation techniques, the proposed DMITNU latch can effectively reduce the number of sensitive nodes. The interlocking connection of two basic modules not only cleverly reduces the number of transistors, thereby lowering circuit overhead, but also enhances the MNU radiation tolerance characteristics of the DMITNU latch. Fault injection methods verified the recovery tolerance of the proposed latch. Compared to advanced TNU tolerant latch designs, the proposed DMITNU latch achieved an average improvement of 61 % in the area-power-delay-product (PDAP). Analysis of PVT variations confirmed that the DMITNU latch maintains good stability under harsh environments. Additionally, Monte Carlo (MC) simulations demonstrated that the DMITNU latch has excellent data storage reliability.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106647"},"PeriodicalIF":1.9,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143686132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A design of lightweight true random number generator based on Galois LFSR with dynamic feedback path 一种基于动态反馈路径的伽罗瓦LFSR的轻量级真随机数发生器设计

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-17 DOI: 10.1016/j.mejo.2025.106652

Zihao Miao , Huaguo Liang , Xin Li , Yingchun Lu , Liang Yao

{"title":"A design of lightweight true random number generator based on Galois LFSR with dynamic feedback path","authors":"Zihao Miao , Huaguo Liang , Xin Li , Yingchun Lu , Liang Yao","doi":"10.1016/j.mejo.2025.106652","DOIUrl":"10.1016/j.mejo.2025.106652","url":null,"abstract":"<div><div>The Linear Feedback Shift Register (LFSR) is a widely utilized circuit structure in electronic systems, often employed as a Pseudo Random Number Generator (PRNG) for generating pseudo random sequence. However, in light of the significant challenges associated with privacy protection and data encryption, traditional PRNGs have frequently failed to meet the increasing security demands of electronic systems. In contrast, True Random Number Generators (TRNGs), have emerged as essential security primitives within the realm of hardware security, garnering increasing attention. In response to these challenges, this paper proposes a novel lightweight TRNG architecture based on Galois LFSR. This innovation design incorporates inverters and two-to-one multiplexers to modify the feedback path. The proposed structure has been implemented on AMD Xilinx Artix-7 and Kintex-7 FPGA boards. Notably, it demonstrates a resource-efficient design, utilizing only 17 Look-Up Tables (LUTs) and 9 D Flip-Flops (DFFs), while achieving random number with throughput of 300Mbps. Furthermore, the structure successfully passes both randomness test and robustness test, indicating its promising application potential in secure electronic systems.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106652"},"PeriodicalIF":1.9,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143644528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A residual pulse broadening interpolation quantization column-level ADC architecture for CMOS image sensors 一种用于CMOS图像传感器的剩余脉冲展宽插值量化列级ADC架构

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-15 DOI: 10.1016/j.mejo.2025.106638

Qiang Zhao , Ziming Wang , Chunhui Fan , Bin Qiang , Jitao Xu , Xin Li , Zhigang Li , Licai Hao , Chunyu Peng , Zhiting Lin , Xiulong Wu

引用次数: 0

Enhanced platform-based interrupt controller for RISC-V MCUs RISC-V mcu的增强型平台中断控制器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-13 DOI: 10.1016/j.mejo.2025.106628

Yang Ren , Nianxiong Tan

{"title":"Enhanced platform-based interrupt controller for RISC-V MCUs","authors":"Yang Ren , Nianxiong Tan","doi":"10.1016/j.mejo.2025.106628","DOIUrl":"10.1016/j.mejo.2025.106628","url":null,"abstract":"<div><div>Interrupt efficiency including latency is a critical factor in the performance of real-time embedded microcontroller units (MCUs) used for the internet of things (IoT). RISC-V MCUs often suffer from greater interrupt latency due to the extensive software intervention required by the conventional Platform-Level Interrupt Controller (PLIC), in contrast to ARM Cortex-M MCUs that employ hardware-accelerated, vectored interrupt handling. Although the Core Local Interrupt Controller (CLIC) has mitigated some latency issues, its lack of native support in many open-source RISC-V cores restricts its widespread adoption. This work introduces an Enhanced PLIC (EPLIC) that incorporates hardware-accelerated features such as vectored scheduling, context saving and restoration, interrupt nesting, and tail-chaining to optimize the Interrupt Service Routine (ISR). Implemented in the open-source Ibex core, EPLIC not only substantially reduces interrupt latency to 7 clock cycles but also achieves interrupt performance on par with commercial MCUs based on ARM’s Cortex-M processors. This work had been implemented in a smart electricity meter System-on-Chip (SoC).</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106628"},"PeriodicalIF":1.9,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143641726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel NMOSFET-embedded high holding voltage SCR for 5-V applications 一种新型的nmosfet嵌入式高保持电压可控硅，适用于5v应用

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-13 DOI: 10.1016/j.mejo.2025.106625

Hongshen Wang , Lingli Qian , Zhiyu Wang , Yuanjie Zhou , Qian Liu , Hao Wu , Jian Shen , Juan Luo , Shengdong Hu

{"title":"A novel NMOSFET-embedded high holding voltage SCR for 5-V applications","authors":"Hongshen Wang , Lingli Qian , Zhiyu Wang , Yuanjie Zhou , Qian Liu , Hao Wu , Jian Shen , Juan Luo , Shengdong Hu","doi":"10.1016/j.mejo.2025.106625","DOIUrl":"10.1016/j.mejo.2025.106625","url":null,"abstract":"<div><div>This study presents a novel NMOSFET-embedded high holding voltage silicon-controlled rectifier (NNEHHVSCR). In this structure, based on the conventional low-trigger SCR with added P+ bridge regions, the NMOSFET is further embedded, supplemented with external electrical connections. This configuration creates multiple ESD current paths to divert current, thereby enhancing the holding voltage. The working principle and <em>I</em>-<em>V</em> characteristic curves of the proposed structure are simulated using Sentaurus TCAD software. The results show that, compared to the reference device, while maintaining a nearly unchanged trigger voltage (<em>V</em><sub>t1</sub>), the NNEHHVSCR significantly increases the holding voltage (<em>V</em><sub>h</sub>) from 3.89 V to 6.03 V, surpassing the lower voltage limit defined by the 5-V ESD design window. Meanwhile, the failure current (<em>I</em><sub>t2</sub>) only decreases slightly from 2.00 A to 1.89 A, with an acceptable trade-off. Therefore, the NNEHHVSCR demonstrates excellent latch-up immunity and ESD robustness, making it suitable for 5-V ESD applications.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106625"},"PeriodicalIF":1.9,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143644527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0