Microelectronics Journal最新文献_第8页

Simulation and fabrication of 4H-SiC SBD with main P-epilayer island termination 带有主p层岛端的4H-SiC SBD的仿真与制作

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-13 DOI: 10.1016/j.mejo.2025.106732

Xinyu Wang , Dengwen Yuan , Shicheng Zhu , Xiyao Huang , Yaxin Li , Lei Ge , Yingxin Cui , Mingsheng Xu , Yu Zhong , Xiaobo Hu , Kuan Yew Cheong , Xiangang Xu , Jisheng Han

{"title":"Simulation and fabrication of 4H-SiC SBD with main P-epilayer island termination","authors":"Xinyu Wang , Dengwen Yuan , Shicheng Zhu , Xiyao Huang , Yaxin Li , Lei Ge , Yingxin Cui , Mingsheng Xu , Yu Zhong , Xiaobo Hu , Kuan Yew Cheong , Xiangang Xu , Jisheng Han","doi":"10.1016/j.mejo.2025.106732","DOIUrl":"10.1016/j.mejo.2025.106732","url":null,"abstract":"<div><div>This article presents the design and fabrication results of 4H-SiC Schottky barrier diode (SBD) with a main P-epilayer island termination. The device simulations analyzed structural parameters, including the island thickness (T<sub>MP</sub>), inclination angle (θ), length (L<sub>MP</sub>), and end relaxation length (L<sub>ER</sub>), on electric field distribution within SBD. Additionally, the influence of the P-type doping concentration (D<sub>MP</sub>) on the breakdown voltage indicates that the main P-epilayer island structure exhibits a relatively wide tolerance range. Using optimal parameters and ion-implantation-free fabrication process, the fabricated SBD with the main P-epilayer island achieved a breakdown voltage of 1543 V with a leakage current of only 1.5 μA under a reverse voltage of 1200 V, and a forward voltage drop (V<sub>F</sub>) of 1.35 V at a forward current of 10 A using the structural parameters of θ = 20°, L<sub>MP</sub> = 104 μm, T<sub>MP</sub> = 1.2 μm, and D<sub>MP</sub> = 6 × 10<sup>17</sup> cm<sup>−3</sup>.This optimized design brings enormous potential for the low-cost development of SBD.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"161 ","pages":"Article 106732"},"PeriodicalIF":1.9,"publicationDate":"2025-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143948163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Electrical properties of fully depleted silicon-on-insulator wafers 完全耗尽绝缘体上硅晶圆的电学特性

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-12 DOI: 10.1016/j.mejo.2025.106731

A.K. Aladim

引用次数: 0

A high charge-discharge stability SRAM 10T1C XOR CIM macro applied in BCAM and Hamming distance 高充放电稳定性SRAM 10T1C XOR CIM宏应用于BCAM和汉明距离

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-10 DOI: 10.1016/j.mejo.2025.106718

Li Liu , Wei Hu , Zhen Yang , Yiming Wei , Chunyu Peng , Xiulong Wu , Zhiting Lin , Wenjuan Lu , Yongliang Zhou , Junning Chen

{"title":"A high charge-discharge stability SRAM 10T1C XOR CIM macro applied in BCAM and Hamming distance","authors":"Li Liu , Wei Hu , Zhen Yang , Yiming Wei , Chunyu Peng , Xiulong Wu , Zhiting Lin , Wenjuan Lu , Yongliang Zhou , Junning Chen","doi":"10.1016/j.mejo.2025.106718","DOIUrl":"10.1016/j.mejo.2025.106718","url":null,"abstract":"<div><div>With the rapid development of artificial intelligence, there has been an increasing demand for computing speed and power. At the same time, computing stability is also essential. We proposed a high charge-discharge stability SRAM 10T1C XOR CIM macro. By decoupling Q and QB nodes, the XOR CIM is completed within the unit without affecting storage stability. Based on the XOR operation, BCAM and Hamming distance are also performed on multiple units in the column. According to the post-layout simulation of 28 nm CMOS process, the standard deviation of 10T1C charge-discharge stability is only 1.236μV at 0.9V, which 6T, 8T, 9T, and 10T are 9.164 mV, 10.329 mV, 16.084 mV and 9.567 mV, respectively. At 0.6V, the accuracy of BCAM reaches 99 %, which is improved by 153.8 %, 291.3 %, 175.8 %, and 206.5 %; the accuracy of Hamming distance reaches 96.8 %, which is improved by 16.3 %, 17.8 %, 16.0 %, and 16.1 %, respectively. This work combine KNN algorithm and Hamming distance to the prediction accuracy of 95.76 % on the MNIST dataset.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"161 ","pages":"Article 106718"},"PeriodicalIF":1.9,"publicationDate":"2025-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143936510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 14-bit 2-MS/s hybrid-logic based SAR ADC with common-mode self-calibration 一种14位2 ms /s混合逻辑的SAR ADC，具有共模自校准功能

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-09 DOI: 10.1016/j.mejo.2025.106724

Sha Li , Qiao Meng , Lizhen Zhang , Jie Wu

{"title":"A 14-bit 2-MS/s hybrid-logic based SAR ADC with common-mode self-calibration","authors":"Sha Li , Qiao Meng , Lizhen Zhang , Jie Wu","doi":"10.1016/j.mejo.2025.106724","DOIUrl":"10.1016/j.mejo.2025.106724","url":null,"abstract":"<div><div>- A 14-bit 2-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) based on hybrid-logic is presented. To enhance the common-mode noise rejection, an inherent common-mode self-calibration technique is proposed without additional calibration circuits. The capacitive digital-to-analog converter (DAC) is partitioned into the most-significant-bit (MSB) segment and the least-significant-bit (LSB) segment, which are controlled by single-ended Fast logic and differential SAR logic, respectively. Two Fast logic circuits generate uncorrelated control codes to switch the MSB segments of the differential DAC, which automatically calibrates the input common-mode voltage of the comparator to ±0.5 LSB of the Fast logic, decreasing the common-mode sensitivity. The wide input common-mode range from 0 to the reference voltage (VREF) is realized. The 14-bit prototype is fabricated in a 180 nm CMOS technology, achieving the signal-to-noise-and-distortion ratio (SNDR) of 81.71 dB and spurious-free dynamic range (SFDR) of 95.57 dB at a sampling rate of 2-MS/s. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.51/-0.57 LSB and +0.52/-0.71 LSB, respectively.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"161 ","pages":"Article 106724"},"PeriodicalIF":1.9,"publicationDate":"2025-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143936511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Performance improvement of gate-all-around (GAA) devices by optimized super-steep retrograde well 优化超陡逆行井对栅极全能器件性能的改善

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-09 DOI: 10.1016/j.mejo.2025.106723

Qingkun Li , Qingzhu Zhang , Lei Cao , Lianlian Li , Xuexiang Zhang , Chuqiao Niu , Guanqiao Sang , Yunjiao Bao , Huaxiang Yin , Zhenhua Wu

引用次数: 0

A fully programmable analog CMOS rational-powered membership function generator with the minimal control signal numbers 一个完全可编程的模拟CMOS理性供电隶属函数发生器与最小的控制信号数

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-08 DOI: 10.1016/j.mejo.2025.106700

Sajjad Moshfe , Fateme Safaei , Neda Enshaei , Majid Salimi , Pourya Hoseini

{"title":"A fully programmable analog CMOS rational-powered membership function generator with the minimal control signal numbers","authors":"Sajjad Moshfe , Fateme Safaei , Neda Enshaei , Majid Salimi , Pourya Hoseini","doi":"10.1016/j.mejo.2025.106700","DOIUrl":"10.1016/j.mejo.2025.106700","url":null,"abstract":"<div><div>In this paper, an analog circuit with minimal control signals for implementing rational-powered membership functions is presented. The proposed circuit is optimized both in terms of continuity and the number of control signals, since we have control the circuit based on analog multpliers. Initially, by equipping our previous fuzzifier with independent control over the rising and falling edges of the membership functions, a novel fuzzifier circuit capable of controlling all parameters with the minimal control signals was proposed. Then, by replacing an analog multiplier instead of the programmable current mirrors, which required a large number of control bits and occupying area, a rational-powered generating module is designed. It should be noted that all required blocks for the fuzzifier and rational-powered generating module were designed in <em>0.</em>18 μm technology and successfully simulated and presented. The proposed circuit has the capability of continuous control over all parameters with minimal control signals. Furthermore, it exhibits the lowest RMS error compared to previously reported works.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"161 ","pages":"Article 106700"},"PeriodicalIF":1.9,"publicationDate":"2025-05-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143928051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A genetic algorithm-based capacitor mismatch calibration scheme for SAR ADCs 基于遗传算法的SAR adc电容失配校正方案

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-07 DOI: 10.1016/j.mejo.2025.106725

Yuzhen Zhang , Xuan Guo , Hanbo Jia , Li Luo , Linzhen Wu , Dandan Wang , Xinyu Liu

{"title":"A genetic algorithm-based capacitor mismatch calibration scheme for SAR ADCs","authors":"Yuzhen Zhang , Xuan Guo , Hanbo Jia , Li Luo , Linzhen Wu , Dandan Wang , Xinyu Liu","doi":"10.1016/j.mejo.2025.106725","DOIUrl":"10.1016/j.mejo.2025.106725","url":null,"abstract":"<div><div>This paper proposes a capacitor mismatch calibration algorithm based on genetic algorithms. The algorithm takes effective number of bits (ENOB) of the analog-to-digital converter (ADC) as the optimization objective, transforms the capacitor mismatch problem into an optimization problem, and solves it using the genetic algorithm. Moreover, a high-energy-efficiency capacitive successive approximation register (SAR) ADC circuit is designed. The capacitive digital-to-analog converter (CDAC) adopts an interdigitated structure, which further reduces capacitor mismatch from the layout aspect. To verify the capacitor mismatch calibration scheme, we conducted experiments on a 312.5 MS/s 6-bit sub-ADC of a time-interleaved ADC designed with a 55-nm CMOS process. The experimental results show that at an input frequency of 150.146 MHz, the ENOB is 5.23 bits and the SFDR is 46.7dBc. Finally, to validate the effectiveness of the proposed scheme for high-precision SAR ADCs, a 14-bit behavioral model was developed to conduct experiments. The experimental results demonstrate an ENOB of 13.2 bits, achieving an improvement of 2.1 bits.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"161 ","pages":"Article 106725"},"PeriodicalIF":1.9,"publicationDate":"2025-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143924870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Curing kinetics of a novel commercial epoxy-phenolic composite build-up film for flip-chip ball grid array (FCBGA) substrates 用于倒装球栅阵列（FCBGA）衬底的新型商用环氧-酚醛复合构筑膜的固化动力学

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-06 DOI: 10.1016/j.mejo.2025.106717

Shanjun Ding, Jingyi Zhao, Xiaomeng Wu, Chuan Chen, Zhidan Fang, Qidong Wang

{"title":"Curing kinetics of a novel commercial epoxy-phenolic composite build-up film for flip-chip ball grid array (FCBGA) substrates","authors":"Shanjun Ding, Jingyi Zhao, Xiaomeng Wu, Chuan Chen, Zhidan Fang, Qidong Wang","doi":"10.1016/j.mejo.2025.106717","DOIUrl":"10.1016/j.mejo.2025.106717","url":null,"abstract":"<div><div>The interface delamination cracking and shrinkage deformation of chip substrates during curing process have influence on reliability. Therefore, curing behaviors in dielectric materials need to be studied to tune the curing process of chiplet substrates and avoid to failure risk. However, the curing behavior of epoxy resin composite build-up films for ultra large size flip chip ball grid array (FCBGA) substrates is not focused so far. Herein, non-isothermal differential scanning calorimetry method is used to study the curing behaviors of epoxy-phenolic composite build-up films by three non-isothermal curing kinetics models and model-free curing models and clarify the curing behavior and mechanism. The results showed that the curing reaction process of the epoxy-phenolic composite film is suit for Kamal curing kinetics model. Three model-free curing models were used to calculate the activating energy at different degree of curing and indicated that activating energy is variable during whole curing process. This work will obviously help to promote substrate warpage simulation and prediction in the future.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"161 ","pages":"Article 106717"},"PeriodicalIF":1.9,"publicationDate":"2025-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143918237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Low-mismatch 20GS/s 5-bit Flash ADC for optical receivers in 90 nm SiGe BiCMOS Technology 用于90 nm SiGe BiCMOS技术光接收机的低失配20GS/s 5位闪存ADC

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-06 DOI: 10.1016/j.mejo.2025.106698

Yinghao Chen , Yingmei Chen , Yizhou Zhao , Chenghao Wu , En Zhu

引用次数: 0

A 2nd-order delta-sigma capacitance-to-digital converter with an embedded error-feedback exponential-incremental noise-shaping SAR quantizer 一种二阶δ - σ电容-数字转换器，内置误差反馈指数增量噪声整形SAR量化器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-05 DOI: 10.1016/j.mejo.2025.106712

Bo Zhao , Yuke Shen , Tao Chen , Yi Shen , Shubin Liu , Ruixue Ding , Zhangming Zhu

{"title":"A 2nd-order delta-sigma capacitance-to-digital converter with an embedded error-feedback exponential-incremental noise-shaping SAR quantizer","authors":"Bo Zhao , Yuke Shen , Tao Chen , Yi Shen , Shubin Liu , Ruixue Ding , Zhangming Zhu","doi":"10.1016/j.mejo.2025.106712","DOIUrl":"10.1016/j.mejo.2025.106712","url":null,"abstract":"<div><div>This paper presents an energy-efficient second-order ΔΣ capacitance-to-digital converter (CDC). A first-order error-feedback exponential-incremental noise-shaping (EF-EINS) successive approximation register (SAR) analog-to-digital converter (ADC) is employed as the multi-bit quantizer. The EF-EINS SAR quantizer using capacitor stacking and dynamic buffering techniques is employed to improve the capacitance resolution. It exhibits superior quantization noise suppression capability compared to the conventional third-order structures with a first-order hardware overhead, significantly reducing the circuit complexity and enhancing the energy efficiency. Verified in a 180-nm CMOS process, simulation results show that the proposed CDC consumes 556.74 μW under a 1.8 V supply at a 5.12 MS/s. It achieves a CDC effective number of bits (ENOB) of 12.5 bits and a capacitance resolution of 25.32 aF within a conversion time of 3.125 μs, exhibiting a CDC Walden figure of merit (FoM<sub>W</sub>) of 0.3 pJ/conv.-step.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"161 ","pages":"Article 106712"},"PeriodicalIF":1.9,"publicationDate":"2025-05-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143924872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0