A Low-mismatch 20GS/s 5-bit Flash ADC for optical receivers in 90 nm SiGe BiCMOS Technology

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-05-06 DOI:10.1016/j.mejo.2025.106698

Yinghao Chen , Yingmei Chen , Yizhou Zhao , Chenghao Wu , En Zhu

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Abstract

This paper presents a 20 GS/s 5-bit flash analog-to-digital converter (ADC) in 90 nm SiGe BiCMOS technology for optical receiver applications. Its architecture includes buffers for input data and clock, tree-based clock network, differential reference ladder (DRL), comparator array, and thermometer code to binary encoder. Track-and-hold amplifier is omitted to reduce complexity and improve linearity. The structure of DRL is a differential amplifier with collector resistor strings. The resistors achieve low mismatch by some layout techniques to quantize input signal uniformly. The encoder is mainly based on multiplexer (MUX) and exclusive-or gate (XOR). The chip occupies a total of 2.35 mm², and consumes 2.45 W from a 3.3 V supply. The measurement results show that the ADC achieves an effective number of bit (ENOB) of 3.24 bit up to Nyquist frequency. The differential non-linearity (DNL) and integral non-linearity (INL) are within ± 0.27 LSB and ± 0.41 LSB, respectively.

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用于90 nm SiGe BiCMOS技术光接收机的低失配20GS/s 5位闪存ADC

本文提出了一种基于90 nm SiGe BiCMOS技术的20gs /s 5位闪存模数转换器（ADC）。其架构包括输入数据和时钟缓冲区、基于树的时钟网络、差分参考阶梯（DRL）、比较器阵列和温度计编码到二进制编码器。跟踪保持放大器省略，以减少复杂性和提高线性度。DRL的结构是带有集电极电阻串的差分放大器。通过对输入信号进行均匀量化，实现了低失配。编码器主要基于多路复用器（MUX）和异或门（XOR）。该芯片的总占地面积为2.35 mm2，在3.3 V电源下功耗为2.45 W。测量结果表明，该ADC在奈奎斯特频率下的有效位元数（ENOB）为3.24位。微分非线性（DNL）和积分非线性（INL）分别在±0.27 LSB和±0.41 LSB以内。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.