Performance improvement of gate-all-around (GAA) devices by optimized super-steep retrograde well

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-05-09 DOI:10.1016/j.mejo.2025.106723

Qingkun Li , Qingzhu Zhang , Lei Cao , Lianlian Li , Xuexiang Zhang , Chuqiao Niu , Guanqiao Sang , Yunjiao Bao , Huaxiang Yin , Zhenhua Wu

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引用次数: 0

Abstract

This paper systematically investigates the super steep retrograde well (SSRW) scheme to improve performance and optimize short-channel effects (SCEs) in vertically stacked multi-nanosheet field-effect transistors (NSFETs). The trade-off between the performance and leakage of super-steep retrograde well NSFETs is systematically investigated through calibrated three-dimensional technology computer-aided design simulations. The advantages of the proposed technique are demonstrated in actual devices, showing a 66 % and 88.2 % reduction in off-state leakage, as well as an 806.78 % and 320.59 % increase in the on-off current ratio of N/P NSFETs. Additionally, there is an improved sub-threshold slope and drain-induced barrier lowering effect. The proposed scheme achieves these performance gains with minimal additional processing complexity, offering a practical strategy for advancing the power efficiency and scalability of GAA architectures.

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优化超陡逆行井对栅极全能器件性能的改善

本文系统地研究了垂直堆叠多纳米片场效应晶体管（nsfet）的超陡逆行井（SSRW）方案，以提高其性能并优化短通道效应（ses）。通过校准的三维技术计算机辅助设计模拟，系统地研究了超陡逆行井nsfet的性能与泄漏之间的权衡。该技术的优点在实际器件中得到了验证，表明N/P nsfet的关断电流比分别提高了806.78%和320.59%，关断电流比分别降低了66%和88.2%。此外，还改善了亚阈值坡度和排水诱导的屏障降低效果。该方案以最小的额外处理复杂性实现了这些性能增益，为提高GAA架构的功率效率和可扩展性提供了一种实用的策略。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.