一种14位2 ms /s混合逻辑的SAR ADC，具有共模自校准功能

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-05-09 DOI:10.1016/j.mejo.2025.106724

Sha Li , Qiao Meng , Lizhen Zhang , Jie Wu

{"title":"一种14位2 ms /s混合逻辑的SAR ADC，具有共模自校准功能","authors":"Sha Li , Qiao Meng , Lizhen Zhang , Jie Wu","doi":"10.1016/j.mejo.2025.106724","DOIUrl":null,"url":null,"abstract":"<div><div>- A 14-bit 2-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) based on hybrid-logic is presented. To enhance the common-mode noise rejection, an inherent common-mode self-calibration technique is proposed without additional calibration circuits. The capacitive digital-to-analog converter (DAC) is partitioned into the most-significant-bit (MSB) segment and the least-significant-bit (LSB) segment, which are controlled by single-ended Fast logic and differential SAR logic, respectively. Two Fast logic circuits generate uncorrelated control codes to switch the MSB segments of the differential DAC, which automatically calibrates the input common-mode voltage of the comparator to ±0.5 LSB of the Fast logic, decreasing the common-mode sensitivity. The wide input common-mode range from 0 to the reference voltage (VREF) is realized. The 14-bit prototype is fabricated in a 180 nm CMOS technology, achieving the signal-to-noise-and-distortion ratio (SNDR) of 81.71 dB and spurious-free dynamic range (SFDR) of 95.57 dB at a sampling rate of 2-MS/s. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.51/-0.57 LSB and +0.52/-0.71 LSB, respectively.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"161 ","pages":"Article 106724"},"PeriodicalIF":1.9000,"publicationDate":"2025-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 14-bit 2-MS/s hybrid-logic based SAR ADC with common-mode self-calibration\",\"authors\":\"Sha Li , Qiao Meng , Lizhen Zhang , Jie Wu\",\"doi\":\"10.1016/j.mejo.2025.106724\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>- A 14-bit 2-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) based on hybrid-logic is presented. To enhance the common-mode noise rejection, an inherent common-mode self-calibration technique is proposed without additional calibration circuits. The capacitive digital-to-analog converter (DAC) is partitioned into the most-significant-bit (MSB) segment and the least-significant-bit (LSB) segment, which are controlled by single-ended Fast logic and differential SAR logic, respectively. Two Fast logic circuits generate uncorrelated control codes to switch the MSB segments of the differential DAC, which automatically calibrates the input common-mode voltage of the comparator to ±0.5 LSB of the Fast logic, decreasing the common-mode sensitivity. The wide input common-mode range from 0 to the reference voltage (VREF) is realized. The 14-bit prototype is fabricated in a 180 nm CMOS technology, achieving the signal-to-noise-and-distortion ratio (SNDR) of 81.71 dB and spurious-free dynamic range (SFDR) of 95.57 dB at a sampling rate of 2-MS/s. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.51/-0.57 LSB and +0.52/-0.71 LSB, respectively.</div></div>\",\"PeriodicalId\":49818,\"journal\":{\"name\":\"Microelectronics Journal\",\"volume\":\"161 \",\"pages\":\"Article 106724\"},\"PeriodicalIF\":1.9000,\"publicationDate\":\"2025-05-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronics Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S1879239125001730\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239125001730","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

摘要

提出了一种基于混合逻辑的14位2 ms /s逐次逼近寄存器（SAR）模数转换器（ADC）。为了增强共模噪声抑制能力，提出了一种无需附加标定电路的固有共模自标定技术。电容式数模转换器（DAC）分为最高有效位（MSB）段和最低有效位（LSB）段，分别由单端Fast逻辑和差分SAR逻辑控制。两个Fast逻辑电路产生不相关的控制代码来切换差分DAC的MSB段，自动校准比较器的输入共模电压到Fast逻辑的±0.5 LSB，降低共模灵敏度。实现了从0到参考电压（VREF）的宽输入共模范围。该14位原型机采用180 nm CMOS技术，在2 ms /s的采样速率下实现了81.71 dB的信噪比和95.57 dB的无杂散动态范围。峰值微分非线性（DNL）和积分非线性（INL）分别为+0.51/-0.57和+0.52/-0.71 LSB。

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A 14-bit 2-MS/s hybrid-logic based SAR ADC with common-mode self-calibration

- A 14-bit 2-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) based on hybrid-logic is presented. To enhance the common-mode noise rejection, an inherent common-mode self-calibration technique is proposed without additional calibration circuits. The capacitive digital-to-analog converter (DAC) is partitioned into the most-significant-bit (MSB) segment and the least-significant-bit (LSB) segment, which are controlled by single-ended Fast logic and differential SAR logic, respectively. Two Fast logic circuits generate uncorrelated control codes to switch the MSB segments of the differential DAC, which automatically calibrates the input common-mode voltage of the comparator to ±0.5 LSB of the Fast logic, decreasing the common-mode sensitivity. The wide input common-mode range from 0 to the reference voltage (VREF) is realized. The 14-bit prototype is fabricated in a 180 nm CMOS technology, achieving the signal-to-noise-and-distortion ratio (SNDR) of 81.71 dB and spurious-free dynamic range (SFDR) of 95.57 dB at a sampling rate of 2-MS/s. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.51/-0.57 LSB and +0.52/-0.71 LSB, respectively.

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.