Simulation and fabrication of 4H-SiC SBD with main P-epilayer island termination

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-05-13 DOI:10.1016/j.mejo.2025.106732

Xinyu Wang , Dengwen Yuan , Shicheng Zhu , Xiyao Huang , Yaxin Li , Lei Ge , Yingxin Cui , Mingsheng Xu , Yu Zhong , Xiaobo Hu , Kuan Yew Cheong , Xiangang Xu , Jisheng Han

{"title":"Simulation and fabrication of 4H-SiC SBD with main P-epilayer island termination","authors":"Xinyu Wang , Dengwen Yuan , Shicheng Zhu , Xiyao Huang , Yaxin Li , Lei Ge , Yingxin Cui , Mingsheng Xu , Yu Zhong , Xiaobo Hu , Kuan Yew Cheong , Xiangang Xu , Jisheng Han","doi":"10.1016/j.mejo.2025.106732","DOIUrl":null,"url":null,"abstract":"<div><div>This article presents the design and fabrication results of 4H-SiC Schottky barrier diode (SBD) with a main P-epilayer island termination. The device simulations analyzed structural parameters, including the island thickness (TMP), inclination angle (θ), length (LMP), and end relaxation length (LER), on electric field distribution within SBD. Additionally, the influence of the P-type doping concentration (DMP) on the breakdown voltage indicates that the main P-epilayer island structure exhibits a relatively wide tolerance range. Using optimal parameters and ion-implantation-free fabrication process, the fabricated SBD with the main P-epilayer island achieved a breakdown voltage of 1543 V with a leakage current of only 1.5 μA under a reverse voltage of 1200 V, and a forward voltage drop (VF) of 1.35 V at a forward current of 10 A using the structural parameters of θ = 20°, LMP = 104 μm, TMP = 1.2 μm, and DMP = 6 × 1017 cm−3.This optimized design brings enormous potential for the low-cost development of SBD.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"161 ","pages":"Article 106732"},"PeriodicalIF":1.9000,"publicationDate":"2025-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S187923912500181X","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

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Abstract

This article presents the design and fabrication results of 4H-SiC Schottky barrier diode (SBD) with a main P-epilayer island termination. The device simulations analyzed structural parameters, including the island thickness (T_MP), inclination angle (θ), length (L_MP), and end relaxation length (L_ER), on electric field distribution within SBD. Additionally, the influence of the P-type doping concentration (D_MP) on the breakdown voltage indicates that the main P-epilayer island structure exhibits a relatively wide tolerance range. Using optimal parameters and ion-implantation-free fabrication process, the fabricated SBD with the main P-epilayer island achieved a breakdown voltage of 1543 V with a leakage current of only 1.5 μA under a reverse voltage of 1200 V, and a forward voltage drop (V_F) of 1.35 V at a forward current of 10 A using the structural parameters of θ = 20°, L_MP = 104 μm, T_MP = 1.2 μm, and D_MP = 6 × 10¹⁷ cm⁻³.This optimized design brings enormous potential for the low-cost development of SBD.

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带有主p层岛端的4H-SiC SBD的仿真与制作

本文介绍了一种主P-epilayer岛端4H-SiC肖特基势垒二极管（SBD）的设计和制造结果。器件仿真分析了结构参数对SBD内部电场分布的影响，包括岛厚度（TMP）、倾角（θ）、长度（LMP）和末端弛豫长度（LER）。此外，p型掺杂浓度（DMP）对击穿电压的影响表明，主p -脱膜岛状结构具有较宽的容差范围。采用最优参数和无离子注入制备工艺，制备的带主p -脱膜岛的SBD在1200 V的反向电压下击穿电压为1543 V，漏电流仅为1.5 μA；当结构参数为θ = 20°，LMP = 104 μm, TMP = 1.2 μm, DMP = 6 × 1017 cm−3时，正向电流为10 a，正向电压降VF为1.35 V。这种优化设计为SBD的低成本开发带来了巨大的潜力。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.