A high charge-discharge stability SRAM 10T1C XOR CIM macro applied in BCAM and Hamming distance

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-05-10 DOI:10.1016/j.mejo.2025.106718

Li Liu , Wei Hu , Zhen Yang , Yiming Wei , Chunyu Peng , Xiulong Wu , Zhiting Lin , Wenjuan Lu , Yongliang Zhou , Junning Chen

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引用次数: 0

Abstract

With the rapid development of artificial intelligence, there has been an increasing demand for computing speed and power. At the same time, computing stability is also essential. We proposed a high charge-discharge stability SRAM 10T1C XOR CIM macro. By decoupling Q and QB nodes, the XOR CIM is completed within the unit without affecting storage stability. Based on the XOR operation, BCAM and Hamming distance are also performed on multiple units in the column. According to the post-layout simulation of 28 nm CMOS process, the standard deviation of 10T1C charge-discharge stability is only 1.236μV at 0.9V, which 6T, 8T, 9T, and 10T are 9.164 mV, 10.329 mV, 16.084 mV and 9.567 mV, respectively. At 0.6V, the accuracy of BCAM reaches 99 %, which is improved by 153.8 %, 291.3 %, 175.8 %, and 206.5 %; the accuracy of Hamming distance reaches 96.8 %, which is improved by 16.3 %, 17.8 %, 16.0 %, and 16.1 %, respectively. This work combine KNN algorithm and Hamming distance to the prediction accuracy of 95.76 % on the MNIST dataset.

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高充放电稳定性SRAM 10T1C XOR CIM宏应用于BCAM和汉明距离

随着人工智能的快速发展，人们对计算速度和计算能力的要求越来越高。同时，计算稳定性也是必不可少的。我们提出了一个高充放电稳定性的SRAM 10T1C XOR CIM宏。通过解耦Q和QB节点，在不影响存储稳定性的情况下，在机组内完成XOR CIM。基于异或运算，BCAM和汉明距离也在列中的多个单元上执行。根据28 nm CMOS工艺布局后仿真，在0.9V时10T1C充放电稳定性的标准差仅为1.236μV，其中6T、8T、9T和10T分别为9.164 mV、10.329 mV、16.084 mV和9.567 mV。在0.6V时，BCAM的精度达到99%，分别提高了153.8%、291.3%、175.8%和206.5%；汉明距离精度达到96.8%，分别提高了16.3%、17.8%、16.0%和16.1%。结合KNN算法和Hamming距离，在MNIST数据集上的预测准确率达到95.76%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.