A genetic algorithm-based capacitor mismatch calibration scheme for SAR ADCs

This paper proposes a capacitor mismatch calibration algorithm based on genetic algorithms. The algorithm takes effective number of bits (ENOB) of the analog-to-digital converter (ADC) as the optimization objective, transforms the capacitor mismatch problem into an optimization problem, and solves it using the genetic algorithm. Moreover, a high-energy-efficiency capacitive successive approximation register (SAR) ADC circuit is designed. The capacitive digital-to-analog converter (CDAC) adopts an interdigitated structure, which further reduces capacitor mismatch from the layout aspect. To verify the capacitor mismatch calibration scheme, we conducted experiments on a 312.5 MS/s 6-bit sub-ADC of a time-interleaved ADC designed with a 55-nm CMOS process. The experimental results show that at an input frequency of 150.146 MHz, the ENOB is 5.23 bits and the SFDR is 46.7dBc. Finally, to validate the effectiveness of the proposed scheme for high-precision SAR ADCs, a 14-bit behavioral model was developed to conduct experiments. The experimental results demonstrate an ENOB of 13.2 bits, achieving an improvement of 2.1 bits.