Microelectronics Journal最新文献_第7页

Highly-selective bandpass filter with enhanced stopband performance based on higher-order triple-mode folded-embedded single-cavity

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2025.106568

Hang Qian , De-Wei Zhang , Qing Liu , Xi Wang , Hai-Lin Deng , Hong-Hui Xu , Lin-Chuan Yang , Dong-Fang Zhou

引用次数: 0

A 7–9 GHz fast-startup low phase noise CMOS LC VCO using Gm-boosted technique and circuit asymmetries for multi-mode radar transmitter

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-01-30 DOI: 10.1016/j.mejo.2025.106586

Tao Tan, Xiuping Li, Yubing Li, Peng Ke

引用次数: 0

A deep oxide trench SOI-LIGBT with self-driving PMOS for improved reliability

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-01-28 DOI: 10.1016/j.mejo.2025.106584

Weizhong Chen, Xiangwei Zeng, Yuting He, Ao Wu

{"title":"A deep oxide trench SOI-LIGBT with self-driving PMOS for improved reliability","authors":"Weizhong Chen, Xiangwei Zeng, Yuting He, Ao Wu","doi":"10.1016/j.mejo.2025.106584","DOIUrl":"10.1016/j.mejo.2025.106584","url":null,"abstract":"<div><div>A novel SOI-LIGBT integrating Self-driving PMOS (SDP) is proposed. The SDP is introduced at the Emitter side which is consists of Deep Oxide Trench (DOT) and lowly Doped P-buried (DP). For the SDP, the Auxiliary Gate (AG) which is shortly connected with the Emitter acts as the gate, and the lowly Doped P-buried (DP), N-drift and P-well act as the source, substrate and drain, respectively. The SDP is designed without additional circuit control, moreover the SDP is driven adaptively along with the working mode of the LIGBT. At the forward conduction, the SDP with <em>V</em><sub>GS</sub> > <em>V</em><sub>th</sub> is turned off and SDP is gradually turned on along with the increasing <em>V</em><sub>CE</sub>, the N-drift substrate of the SDP creates an electrical channel for hole carriers to let the hole currents divert. At the turning off, the SDP with <em>V</em><sub>GS</sub> < <em>V</em><sub>th</sub> is turned on again to extract the excessive hole carriers. Hence, the PDP-LIGBT achieves superior short reliability. As a result, the short circuit tolerance time of PDP-LIGBT reaches to 6.98 μs, and the <em>E</em><sub>OFF</sub> is decreased by 18.5 % and 22.2 % under the same <em>V</em><sub>ON</sub> of 1.22 V when compared with the DOT-LIGBT, and DP-LIGBT.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"157 ","pages":"Article 106584"},"PeriodicalIF":1.9,"publicationDate":"2025-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143141288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Exact and approximate Radix-4 recoding multipliers for high-efficiency computation

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-01-23 DOI: 10.1016/j.mejo.2025.106579

Xinyu Zhu, Hongge Li, Yinjie Song

引用次数: 0

Study of GaN Schottky barrier IMPATT diodes with a self-aligned field plate for terahertz applications

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-01-22 DOI: 10.1016/j.mejo.2025.106572

Xuan Huang, Lin-An Yang, Jian-Hua Zhou, Xin-Yi Wang, Xiao-Hua Ma, Yue Hao

引用次数: 0

A calibration scheme for SAR ADCs based on capacitor weight optimization using an improved simulated annealing algorithm

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-01-21 DOI: 10.1016/j.mejo.2025.106583

Zhuofan Wang , Lili Lang , Wei Zhong , Yi Shan , Zhongying Xue , Yemin Dong

{"title":"A calibration scheme for SAR ADCs based on capacitor weight optimization using an improved simulated annealing algorithm","authors":"Zhuofan Wang , Lili Lang , Wei Zhong , Yi Shan , Zhongying Xue , Yemin Dong","doi":"10.1016/j.mejo.2025.106583","DOIUrl":"10.1016/j.mejo.2025.106583","url":null,"abstract":"<div><div>This paper proposes a foreground calibration method, which applies simulated annealing (SA) algorithm to the calibration of successive approximation register analog-to-digital converters (SAR ADCs). The capacitor weights are updated according to the performance metrics of the output codes, without necessitating any signal injection or modifying the analog structure of the SAR ADC. The methods of iterative and parallel solving, as well as variable searching step size are introduced into the SA calibration for adequate search. In addition, a multi-objective optimization strategy based on lexicographic optimization is used to take into account the performance of both signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR). The estimated capacitor weights are applied in the digital domain to calibrate the SAR ADC output codes. The effectiveness of this calibration method is verified by simulating a 12-bit SAR ADC model with 2-bit redundancy and calibrating a 16-bit, 500 kS/s SAR ADC with 4-bit redundancy fabricated in 180 nm technology. The simulation results show the significant improvements in both SNDR and SFDR, along with a notable enhancement in integral nonlinearity (INL). 512 sinusoidal signal samples are collected on testing platform to extract the capacitor weights that can further contribute to the calculation of the output codes. The experiment results show that the SNDR and SFDR are improved by 20.04 dB and 20.19 dB, respectively, while the INL are enhanced by nearly 16 LSB.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"157 ","pages":"Article 106583"},"PeriodicalIF":1.9,"publicationDate":"2025-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143097071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Simulation study of inversion, accumulation, and junctionless mode monolayer MoS2/Ge heterojunction nanosheet at 1.5 nm node

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-01-20 DOI: 10.1016/j.mejo.2024.106550

Xia Guo , Xinlong Shi , Ying Wang

{"title":"Simulation study of inversion, accumulation, and junctionless mode monolayer MoS2/Ge heterojunction nanosheet at 1.5 nm node","authors":"Xia Guo , Xinlong Shi , Ying Wang","doi":"10.1016/j.mejo.2024.106550","DOIUrl":"10.1016/j.mejo.2024.106550","url":null,"abstract":"<div><div>This paper evaluates the performance of monolayer MoS<sub>2</sub>/Ge heterojunction n-channel nanosheet (MGHJFET) in various operating modes, including inversion mode (IM), accumulation mode (AC), and junctionless mode (JL), at the 1.5 nm technology node. To investigate these MGHJFET characteristics, a hybrid simulation approach was employed, combining atomistic simulations using density functional theory (DFT) with technology-computer-aided design (TCAD) simulations. The electrical characteristics of three types of MGHJFETs with different channel doping levels were analyzed. Further assessment was conducted on the analog and digital performance of the MGHJFETs in IM, AC, and JL modes. The IM and AC MGHJFETs exhibit superior performance due to current modulation in the monolayer MoS<sub>2</sub>. Specifically, the saturation current in IM and AC structures reaches up to <span><math><mrow><mn>8</mn><mo>.</mo><mn>5</mn><mo>×</mo><mn>1</mn><msup><mrow><mn>0</mn></mrow><mrow><mo>−</mo><mn>5</mn></mrow></msup></mrow></math></span> A, and the <span><math><msub><mrow><mi>I</mi></mrow><mrow><mi>on</mi></mrow></msub></math></span>/<span><math><msub><mrow><mi>I</mi></mrow><mrow><mi>off</mi></mrow></msub></math></span> ratio achieves <span><math><mrow><mn>1</mn><msup><mrow><mn>0</mn></mrow><mrow><mn>6</mn></mrow></msup></mrow></math></span>. By utilizing the 2D monolayer MoS<sub>2</sub> material, the channel current of IM and AC MGHJFETs can be effectively modulated. Combined with the other advantages of 2D materials, this device is capable of scaling down to its smallest possible physical limits in the post-Moore era.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"157 ","pages":"Article 106550"},"PeriodicalIF":1.9,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143097072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 0.87-ppm/°C, 3.2−40 V VIN reference voltage source with −121 dB PSRR at 100 Hz

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-01-20 DOI: 10.1016/j.mejo.2025.106560

Chunlai Wang , Ying Zhang , Chen Yang , Yuchi Xiao , Hongyang Hou , Weihua Han

引用次数: 0

A 10 Gb/s PAM4 receiver with reference-less half-rate Bang-Bang CDR in 180-nm CMOS

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-01-20 DOI: 10.1016/j.mejo.2025.106580

Jiaxin Liu , Yinhang Zhang , Chao Yin , Xi Yang , Yongzheng Zhan

{"title":"A 10 Gb/s PAM4 receiver with reference-less half-rate Bang-Bang CDR in 180-nm CMOS","authors":"Jiaxin Liu , Yinhang Zhang , Chao Yin , Xi Yang , Yongzheng Zhan","doi":"10.1016/j.mejo.2025.106580","DOIUrl":"10.1016/j.mejo.2025.106580","url":null,"abstract":"<div><div>This paper discusses a 10 Gb/s PAM4 wireline receiver that employs bandwidth compensation in analog front-end (AFE), high performance half rate data recovery circuit and clock recovery circuit without reference clock. The combination of continuous-time linear equalizer (CTLE) with peaking inductance and transimpedance amplifier (TIA) based on inverter improves the bandwidth and gain of AFE. Level shifter and limiting amplifier (LA) achieve the conversion of multi-level signals to thermometer codes and reduces the accuracy or adaptive requirements of comparator threshold voltage. The jitter of clock recovery circuit is effectively reduced by the half rate Bang-Bang phase detector (BBPD), and quadrature LC-voltage-controlled oscillator (LC-VCO) guarantees the low jitter of recovered clock. The post-simulation results show that the receiver can provide as much as 6.086 dB equalization. The core of the receiver occupies 1.25 × 0.84 mm<sup>2</sup> area and consumes 195.42 mW power at the supply voltage of 1.8 V. The horizontal opening degree of recovered 2.5 Gb/s data reaches 0.8 UI and the jitter of recovered 2.5 Gb/s clock is 11.76 ps.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"157 ","pages":"Article 106580"},"PeriodicalIF":1.9,"publicationDate":"2025-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143141286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of high suppression filter for millimeter-wave using glass-based advanced package integrated technology

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-01-17 DOI: 10.1016/j.mejo.2025.106567

Yanzhu Qi, Yazi Cao, Shichang Chen, Gaofeng Wang

{"title":"Design of high suppression filter for millimeter-wave using glass-based advanced package integrated technology","authors":"Yanzhu Qi, Yazi Cao, Shichang Chen, Gaofeng Wang","doi":"10.1016/j.mejo.2025.106567","DOIUrl":"10.1016/j.mejo.2025.106567","url":null,"abstract":"<div><div>A high-selective millimeter-wave bandpass filter (BPF) utilizing folded-line coupling resonator (FLCR) is presented. This BPF consists of four unitized FLCRs, which are realized by redistribution layer (RDL) on a glass interposer. There are electric and magnetic couplings among the resonators. By parameterizing the size and couplings of the FLCRs, the passband and four TZs can be readily controlled. To illustrate the operational principle, an equivalent circuit of the FLCRs is proposed and discussed. To validate the design, the BPF prototype working at 20.7 GHz is designed and fabricated. The measured results show that the designed BPF can achieve a 3-dB fractional bandwidth of 17.3 %. Moreover, the designed BPF exhibits a roll-off of 18.68 dB/GHz in the low sideband and a roll-off of 10.76 dB/GHz in the high sideband, thereby producing sharp-rejection filtering. In addition, it can achieve more than 36 dB of suppression from 0 to 14.6 GHz and more than 30 dB from 24.5 to 38.5 GHz. The fabricated BPF has a compact size of 1.73 mm × 1.1 mm (0.242 λg × 0.154 λg).</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"157 ","pages":"Article 106567"},"PeriodicalIF":1.9,"publicationDate":"2025-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143097068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0