Microelectronics Journal最新文献

{"title":"A −184 dB PSRR and 2.47 μVrms noise self biased bandgap reference based on FVF structure","authors":"Jin Xie ,&nbsp;Chunkai Wu ,&nbsp;Junyuan Wu ,&nbsp;Jinghu Li ,&nbsp;Zhicong Luo ,&nbsp;Qiyan Sun","doi":"10.1016/j.mejo.2024.106388","DOIUrl":"10.1016/j.mejo.2024.106388","url":null,"abstract":"<div><p>A high power supply rejection ratio (PSRR), low noise and low-power self-biased bandgap voltage reference (BGR) is presented in this paper. In response to the trade-off between power consumption and output noise, a feedback depth enhancement technique is proposed for mitigating the effect of the resistor on output noise and offset voltage. The PSRR is enhanced by a novel self regulating technology based on an improved flipped voltage follower (FVF). The designed BGR was verified under post-simulation for various process corners, voltages and temperatures (PVT). It was using <span><math><mrow><mn>0</mn><mo>.</mo><mn>18</mn><mspace></mspace><mi>μ</mi><mi>m</mi></mrow></math></span> BiCMOS process, occupying an active area of 0.016 mm<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span>. The BGR operates normally at 3.0 V – 3.6 V with a quiescent current of 3.6 <span><math><mi>μ</mi></math></span>A. The best untrimmed TC is 22.04 ppm<span><math><mrow><msup><mrow><mo>/</mo></mrow><mrow><mo>∘</mo></mrow></msup><mi>C</mi></mrow></math></span> and the rms noise is only 2.47 <span><math><mrow><mi>μ</mi><msub><mrow><mi>V</mi></mrow><mrow><mi>r</mi><mi>m</mi><mi>s</mi></mrow></msub></mrow></math></span> from 0.1 Hz to 10 Hz. The PSRR is −184 dB@1 Hz and −50 dB@1 MHz when <span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>I</mi><mi>N</mi></mrow></msub></math></span> = 3.0 V.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142058151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A reconfigurable FPGA-based spiking neural network accelerator","authors":"Mingqi Yin ,&nbsp;Xiaole Cui ,&nbsp;Feng Wei ,&nbsp;Hanqing Liu ,&nbsp;Yuanyuan Jiang ,&nbsp;Xiaoxin Cui","doi":"10.1016/j.mejo.2024.106377","DOIUrl":"10.1016/j.mejo.2024.106377","url":null,"abstract":"<div><p>The spiking neural network (SNN) is suitable for the intelligent edge computing applications because of its low-power characteristic. This work designs a reconfigurable spiking neural network accelerator supporting the spatiotemporal backpropagation (STBP) training method. The reconfigurable architecture is proposed between the spatial convolution module and the temporal accumulation module of the SNN accelerator. A sparse zero-hopping mechanism is designed to exploit the input sparsity of SNN datasets, and a mask mechanism is introduced between the forward inference computation and the backward training computation to exploit the output sparsity. During the training process, the peak and average performances of the SNN accelerator are 5.57 TOPS and 4.96 TOPS respectively, the power consumption is 6.124 W and the energy efficiency is 0.81 TOPS/W. The peak and average performances of the SNN accelerator are 5.98 TOPS and 5.14 TOPS respectively, the power consumption is 6.943 W and the energy efficiency is 0.74 TOPS/W, during the inference process.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142075989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A chopper instrumentation amplifier with discrete-time compensation based on current generation unit to eliminate electrode DC offset","authors":"Zichao Wang ,&nbsp;Kui Wen ,&nbsp;Ruixue Ding ,&nbsp;Shubin Liu ,&nbsp;Zhangming Zhu","doi":"10.1016/j.mejo.2024.106375","DOIUrl":"10.1016/j.mejo.2024.106375","url":null,"abstract":"<div><p>A capacitively-coupled chopper instrumentation amplifier (CCIA) for bio-potential signals acquisition is proposed in this paper. A novel discrete-time compensation scheme based on the current generation unit is adopted to suppress the DC offset caused by the sampling electrode. Different with the traditional analog DC servo loop (DSL) used in previous works, the circuit based on this scheme is more straightforward and consumes less power. Moreover, it can suppress a larger electrode DC offset in a short time. This work is designed in a standard 180 nm CMOS process. The CCIA operates from a 1.8 V supply, from which it draws a total current of 0.72 <span><math><mi>μ</mi></math></span>A. The simulation result shows that the signal bandwidth of the proposed CCIA is 1.2 – 500 Hz and the mid-band gain is about 31.49 dB. In the frequency band of 1 – 500 Hz, the input-referred noise of the circuit is 2.01 <span><math><mrow><mi>μ</mi><msub><mrow><mi>V</mi></mrow><mrow><mi>r</mi><mi>m</mi><mi>s</mi></mrow></msub></mrow></math></span>. Inputting a single-tone sine wave with an amplitude of 14.1 mV at the frequency of 56.152 Hz, the total harmonic distortion (THD) of the CCIA’s output is −51.38 dB. This circuit can suppress a large electrode DC offset within a few milliseconds, and the maximum electrode DC offset that can be tolerated up to 130 mV.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142050444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Variation-aware automated design and optimization of sub-1V bandgap voltage reference","authors":"Abdelrahman A. Mohammad ,&nbsp;Mohamed A.Y. Abdalla ,&nbsp;Hesham Omran","doi":"10.1016/j.mejo.2024.106373","DOIUrl":"10.1016/j.mejo.2024.106373","url":null,"abstract":"<div><p>A robust systematic gm/ID-based design procedure for a CMOS low-voltage bandgap reference is introduced. The proposed approach is technology node independent, and it eliminates invoking the simulator in the loop by using precomputed lookup tables (LUTs) generated once. The proposed methodology is capable of addressing the impact of PVT corners and random mismatch. The proposed procedure is verified against Spectre simulations and yields very accurate results. Moreover, the bandgap reference automated synthesis procedure is fully vectorized, enabling the concurrent synthesis of multiple design points in a short time. As a result, large datasets can be generated to span the whole design space, which enables global optimization. Next, local optimization algorithms can be utilized to quickly determine the degrees of freedom of an optimal design point that meets a set of specifications. The speedup of the proposed methodology is around 140x compared to simulation-based optimization in addition to accomplishing better results.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142075988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Simulation study on temperature characteristics of AlN/ β-Ga2O3 HEMT","authors":"Xiaomin He ,&nbsp;Haitao Zhang ,&nbsp;Liqiao Wu ,&nbsp;Jichao Hu ,&nbsp;Min Lu ,&nbsp;Lei Yuan","doi":"10.1016/j.mejo.2024.106386","DOIUrl":"10.1016/j.mejo.2024.106386","url":null,"abstract":"<div><p>This paper reports a comprehensive analysis of temperature on DC and AC characteristics of AlN/β-Ga₂O₃ HEMT. As the temperature increases from 300 °C to 500 °C, the drain current (<em>I</em>_<em>DS</em>) decreases by 50 %, leading to a 50 % decrease in transconductance (<em>g</em>_<em>m</em>) without self heating effect. This decrease in maximum <em>g</em>_<em>m</em> further resulted in a significant reduction of 49 % in the cut-off frequency (<em>f</em>_<em>T</em>). Incorporating the self-heating effect, while the threshold voltage (<em>V</em>_<em>th</em>) remains unaffected, the maximum <em>g</em>_<em>m</em> experiences a marked decrease. At 300 °C, the decrease reaches 58 %, while at 500 °C, the decrease is 36 %. Additionally, the saturation <em>I</em>_<em>DS</em> shows a negative differential resistance phenomenon. Furthermore, the decrease at 300°Cin <em>f</em>_<em>T</em> reaches 45 %, while at 500 °C, the decrease is 30 %. The main reason for the performance degradation caused by self heating effect at low temperatures is that the peak temperature at the channel of the device increases more significantly at low temperatures, resulting in a more significant decrease in mobility.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142084239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Memory architecture to mitigate side channel attacks for cryptographic application using loop cut technique","authors":"Aastha Gupta,&nbsp;Ravi Sindal,&nbsp;Vaibhav Neema","doi":"10.1016/j.mejo.2024.106374","DOIUrl":"10.1016/j.mejo.2024.106374","url":null,"abstract":"<div><p>Cryptography is crucial in embedded systems for safeguarding sensitive information, maintaining data integrity, and facilitating secure communication. L1 cache memory enhances overall performance by temporarily storing cryptographic keys. Post-quantum cryptography (PQC) focuses on creating algorithms that stay secure even against quantum computing threats. However, PQC doesn't fully protect against side-channel attacks (SCA). As IoT devices like wearable health monitors and industrial sensors become more widespread, the demand for lightweight cryptography increases to balance security with resource constraints. Yet, lightweight cryptography can face challenges, including reduced security and increased susceptibility to SCA due to smaller key sizes. Attackers can exploit power consumption patterns through side-channel attacks (SCA), such as Power Analysis, to extract these secret keys. Once a key is compromised, encrypted data becomes vulnerable. In cloud computing cache side-channel attacks take advantage of multiple virtual machines running simultaneously on the same hardware, enabling them to extract sensitive information from encryption processes. Although many SRAM cells have been designed in the literature, none offer complete security against SCA. This paper presents a new architecture for secure cache memory using a proposed 10T SRAM cell that secures all three cell operations (read, write, and hold) against SCA attacks. Additionally, this architecture also prevents half selection issue in cache memory. The security measure of proposed-10T cell is 97.19 % which is highest among all other cells and reliability measure is 82.03 %.The cell also offers highest hold stability of 421 mV along with good read stability and write ability of 220 mV and 334 mV respectively. The leakage of Proposed-10T cell is also less i.e., 13.56 pA. The Performance and Security Factor (PSF) is computed for all considered cells, encompassing various performance and security metrics. The normalized PSF (PSF)_N of the Proposed-10T cell is 2.17, the highest among all cells considered for comparison. Therefore, the Proposed-10T cell architecture is fully secure against SCA and achieves better performance during cell operations.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142049199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Asymmetric CMOS switch for Dicke radiometer in millimeter-wave imaging system","authors":"Joon-Hyuk Yoon,&nbsp;Ha-Neul Lee,&nbsp;Ui-Gyu Choi,&nbsp;Jong-Ryul Yang","doi":"10.1016/j.mejo.2024.106372","DOIUrl":"10.1016/j.mejo.2024.106372","url":null,"abstract":"<div><p>An asymmetric Dicke switch implemented in bulk complementary metal-oxide-semiconductor (CMOS) technology is proposed to achieve high isolation and low insertion loss in the D-band. A Dicke switch eliminates the noise in the signal transmitted from the antenna, providing a high signal-to-noise ratio at the receiver front end. The proposed Dicke switch employs an asymmetric configuration for the signal transmission path and the reference noise incidence path, which overcomes the trade-off relationship between the insertion loss and isolation characteristics. The proposed asymmetric structure presents an optimum impedance in the reference component to achieve the same characteristics as those of the noise incident from the antenna port. The Dicke switch is fabricated using the 65-nm RFCMOS process with a chip size of 350 × 490 μm², including all the pads. The measurement results in the D-band present an insertion loss below 2.8 dB in the on-state and isolation above 22 dB in the off-state. The minimum insertion loss and maximum isolation were measured to be 1.7 dB at 155 GHz and 29 dB at 122 GHz, respectively.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142011240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electroless silver plating on through-glass via (TGV) as an adhesive and conducting layer","authors":"Yuxuan Huang ,&nbsp;Zhihua Tao ,&nbsp;Xudong Cai ,&nbsp;Zhiyuan Long ,&nbsp;Zewei Lin ,&nbsp;Wenlei Li ,&nbsp;Zhen Fang ,&nbsp;Lingyue Wang ,&nbsp;Siqi He ,&nbsp;Xingzhou Cai ,&nbsp;Yong Li ,&nbsp;Jihua Zhang","doi":"10.1016/j.mejo.2024.106371","DOIUrl":"10.1016/j.mejo.2024.106371","url":null,"abstract":"<div><p>The proposed method presents a scheme to modify the surface of the glass substrate using the piranha solution and to fabricate the conducting layer of the Through-glass Via (TGV) by the glucose-Ag electroless plating to achieve TGV metallization. The arithmetic mean deviation of the surface contours (Ra) for the substrates increases from 0.001 to 0.135. The contact angle of the substrates (unmodified and modified) is reduced to 6.4° and 12.2°, respectively. The sensitization process with SnCl₂ and the activation process with silver ammonia solution are conducted using the glucose as the reducing agent to prepare the silver seed layer covered in the TGV through-vias with a high aspect ratio (9:1). The adhesion between the metal coating and the surface is measured by the 3M tape and chemical mechanical polishing (CMP). The metal coating adheres well to the surface-modified substrate without peeling off, which can satisfy the demands for the electroplating and CMP processes.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142044935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An approximate dynamic model of double-sided LCC resonant converter in wireless power transmission based on average current model","authors":"Zhiwei Chen ,&nbsp;Xinjie Zhao ,&nbsp;Qipei Zhou ,&nbsp;Tingli Cheng ,&nbsp;Xiang Li ,&nbsp;Yujiao Zhang","doi":"10.1016/j.mejo.2024.106370","DOIUrl":"10.1016/j.mejo.2024.106370","url":null,"abstract":"<div><p>Wireless Power Transmission (WPT) system could realize a non-contact power transmission through the air gap weak magnetic coupling. This paper aims at analyzing a dynamic model of the WPT system based on a double-side LCC. Firstly, in the multivariable framework, the dynamic characteristics of double-side LCC resonant compensation topology are analyzed by the mutual inductance model. The approximate small-signal model of double-side LCC resonant converter is derived by generalized state-space averaging (GSSA). Additionally, a double-side LCC compensation topology based on double closed-loop average current mode control approach is proposed. By contrasting the behavior of the WPT system under various operating conditions, the efficacy of the suggested dynamic model is illustrated. Finally, a wireless power transmission system experiment platform with a resonant frequency of 85 kHz and an output power of 3 kW was built. Through the experiments, it is determined that the model has a certain ability to predict the dynamic behavior of the wireless charging system. So, it can be utilized as a useful instrument for the transient's analysis and the controller development optimization.</p><p>© 2017 Elsevier Inc. All rights reserved.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142040598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multi-switch-controlled multi-mode TRFE with a high-linearity ATRSW for 2.4-GHz ISM applications","authors":"Libo Zheng ,&nbsp;Yan Jiang ,&nbsp;Haowei Xie ,&nbsp;Xiaohuan Li ,&nbsp;Hualong Ji ,&nbsp;Yi Liu ,&nbsp;Yufeng Guo","doi":"10.1016/j.mejo.2024.106368","DOIUrl":"10.1016/j.mejo.2024.106368","url":null,"abstract":"<div><p>This paper presents a multi-switch-controlled multi-mode transceiver front end (TRFE) designed for the 2.4-GHz industrial–scientific–medical (ISM) band, with a particular focus on enhancing the linearity of the transmit/receive switch (TRSW) on the antenna side. Considering the distinct power levels in the RX/TX paths, the TRSW is designed to be asymmetric. This design not only elevates IP_-0.1dB by over 50 % compared to the conventional symmetric topology, but also absorbing its function into the input matching network (IMN) of the low noise amplifier (LNA), thereby minimally impacting the noise figure (NF) of the RX chain. For the TX path, the high-pass component of the power amplifier (PA) output matching network (OMN) is repurposed, with a singular inductor being redeployed to serve as an inductive ESD safeguard. Moreover, the driving stage employs a passive gain-boosting technique, which elevates the gain by 3 dB compared to the traditional cascode structure. For verification, this TRFE is fabricated in 0.18-μm CMOS with a die size of 1.53 mm². It achieves a NF of 2.4 dB and a RX gain of 16.7 dB under a 3.3-V supply. A TX gain of 26.2 dB and a saturation output power of 23.3 dBm with a peak power-added efficiency (PAE) of 38.8 % are also demonstrated.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141984847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}