Microelectronics Journal最新文献_第7页

N-DIBL optimization of NC-GAAFET NW for low power fast switching applications 针对低功耗快速开关应用的 NC-GAAFET NW 的 N-DIBL 优化

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-24 DOI: 10.1016/j.mejo.2024.106321

引用次数: 0

A 0.91-μA-quiescent-current capacitor-less LDO with sub-threshold transient enhancement and bulk-driven feed-forward supply ripple cancellation 静态电流为 0.91μA 的无电容 LDO，具有亚阈值瞬态增强和批量驱动前馈电源纹波消除功能

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-23 DOI: 10.1016/j.mejo.2024.106311

{"title":"A 0.91-μA-quiescent-current capacitor-less LDO with sub-threshold transient enhancement and bulk-driven feed-forward supply ripple cancellation","authors":"","doi":"10.1016/j.mejo.2024.106311","DOIUrl":"10.1016/j.mejo.2024.106311","url":null,"abstract":"<div>This paper presents a capacitor-less low-dropout (OCL-LDO) regulator that features a low quiescent current for low power applications. To enhance the transient response of proposed OCL-LDO, a sub-threshold transient enhancement circuit including a transient signal input stage, a current subtractor, and a current amplifier is suggested. Meanwhile, a circuit made up of a bulk-driven ripple feed-forward circuit and a ripple introduction circuit is developed in order to improve PSR of the OCL-LDO. The proposed OCL-LDO is fabricated in 0.18 <math><mi>μ</mi></math>m standard CMOS process and has an active area of 0.053 mm2. Based on measurement results, the proposed OCL-LDO has a maximum load current of 100 mA at 1.2 V input and 1 V output, and a minimum quiescent current of 0.91 <math><mi>μ</mi></math>A. The overshoot voltage and undershoot voltage are 199 mV and 204 mV, respectively. PSR of the OCL-LDO is <math><mo>−</mo></math>71.8 dB at 1 KHz when the load current is 100 mA. Furthermore, the OCL-LDO exhibits a load regulation of 11.1 <math><mi>μ</mi></math>V/mA and a line regulation of 1.05 mV/V.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141849731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A reconfigurable multi-precision quantization-aware nonlinear activation function hardware module for DNNs 用于 DNN 的可重构多精度量化感知非线性激活函数硬件模块

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-22 DOI: 10.1016/j.mejo.2024.106346

{"title":"A reconfigurable multi-precision quantization-aware nonlinear activation function hardware module for DNNs","authors":"","doi":"10.1016/j.mejo.2024.106346","DOIUrl":"10.1016/j.mejo.2024.106346","url":null,"abstract":"<div>In recent years, the increasing variety of nonlinear activation functions (NAFs) in deep neural networks (DNNs) has led to higher computational demands. However, hardware implementation faces challenges such as lack of flexibility, high hardware cost, and limited accuracy. This paper proposes a highly flexible and low-cost hardware solution for implementing activation functions to overcome these issues. Based on the piecewise linear (PWL) approximation method, our method supports NAFs with different accuracy configurations through a customized implementation strategy to meet the requirements in different scenario applications. In this paper, the symmetry of the activation function is investigated, and incorporate curve translation preprocessing and data quantization to significantly reduce hardware storage costs. The modular hardware architecture proposed in this study supports NAFs of multiple accuracies, which is suitable for designing deep learning neural network accelerators in various scenarios, avoiding the need to design dedicated hardware circuits for the activation function layer and enhances circuit design efficiency. The proposed hardware architecture is validated on the Xilinx XC7Z010 development board. The experimental results show that the average absolute error (AAE) is reduced by about 35.6 % at a clock frequency of 312.5 MHz. Additionally, the accuracy loss of the model is maximized to −0.684 % after replacing the activation layer function of DNNs under the PyTorch framework.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141841666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Ambipolar current suppression in drain elevated TFET using a novel extended drain structure with a moderate doping profile 利用具有适度掺杂特征的新型扩展漏极结构抑制漏极升高型 TFET 中的两极电流

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-22 DOI: 10.1016/j.mejo.2024.106302

{"title":"Ambipolar current suppression in drain elevated TFET using a novel extended drain structure with a moderate doping profile","authors":"","doi":"10.1016/j.mejo.2024.106302","DOIUrl":"10.1016/j.mejo.2024.106302","url":null,"abstract":"<div>In this paper, a simple and compact silicon-based Elevated and Extended Drain with Hetero-Dielectric Gate Oxide TFET (EED HDGO TFET) is proposed to suppress the ambipolar current in Elevated Drain TFET (ED TFET). The proposed device structure uses a moderately doped drain with a doping concentration of <math><mo>∼</mo></math>1018 cm−3 and a high drain length of <math><mo>∼</mo></math>50–100 nm. The combination of the moderate drain doping profile and the extended drain length reduced the impact of the electrostatic potential from the positive voltage of the drain electrode on the channel–drain junction. This structural technique widens the tunneling width at the channel–drain region causing the tunneling current to decrease significantly. The tunneling width is further increased by structurally isolating the channel–drain junction region from the gate electrode. Thus, distancing the channel–drain junction from both the gate electric field and the static drain potential of the drain electrode causes full suppression of the ambipolar (Iamb) current. The proposed structure yields Iamb and Ioff as low as <math><mo>∼</mo></math>10−18 A/<math><mrow><mi>μ</mi><mi>m</mi></mrow></math> and <math><mo>∼</mo></math>10−17 A/<math><mrow><mi>μ</mi><mi>m</mi></mrow></math> respectively, while maintaining the Ion as <math><mo>∼</mo></math>0.3 mA. The device is optimized for low power and high-speed digital circuits through intensive parametric analysis on gate–drain Cgd and the gate–source Cgs capacitances for various device parameters.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141852291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An 8b-Precison 16-Kb FDSOI 8T SRAM CIM macro based on time-domain for energy-efficient edge AI devices 基于时域的 8b-precison 16-Kb FDSOI 8T SRAM CIM 宏，用于高能效边缘人工智能设备

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-21 DOI: 10.1016/j.mejo.2024.106308

引用次数: 0

An auto-zeroing chopper-stabilized capacitively coupled instrumentation amplifier with 25-Vpp common-mode interference tolerance 具有 25 Vpp 的自动归零斩波稳定电容耦合仪表放大器</mml:msub

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-20 DOI: 10.1016/j.mejo.2024.106303

引用次数: 0

Genetic neural network based background calibration method for pipeline ADC 基于遗传神经网络的管道 ADC 背景校准方法

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-20 DOI: 10.1016/j.mejo.2024.106317

引用次数: 0

Source/drain extension asymmetric counter-doping for suppressing channel leakage in stacked nanosheet transistors 源极/漏极扩展非对称反掺杂抑制叠层纳米片晶体管中的沟道泄漏

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-20 DOI: 10.1016/j.mejo.2024.106347

引用次数: 0

Quantized CNN-based efficient hardware architecture for real-time hand gesture recognition 基于量化 CNN 的实时手势识别高效硬件架构

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-19 DOI: 10.1016/j.mejo.2024.106345

引用次数: 0

An ICMR-enhanced three-opamp instrumentation amplifier ICMR 增强型三功放仪表放大器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-07-18 DOI: 10.1016/j.mejo.2024.106342

{"title":"An ICMR-enhanced three-opamp instrumentation amplifier","authors":"","doi":"10.1016/j.mejo.2024.106342","DOIUrl":"10.1016/j.mejo.2024.106342","url":null,"abstract":"<div>The three-operational amplifiers (three-opamp) structure is a widely used topology to design precision instrumentation amplifiers (IAs). However, the input common-mode range (ICMR) of the classical three-opamp IA is limited to the output voltage range of the internal operational amplifiers, resulting in the output voltage range being constrained by the input common-mode voltage. This article proposes an ICMR-enhanced three-opamp topology, which constructs a common-mode feedback (CMFB) loop at the first stage of the IA, enabling the first stage has the capability of common-mode rejection. Hence, the proposed ICMR-enhanced three-opamp IA overcomes the limitation of ICMR, eliminates the constraint of the output voltage range and improves the common-mode rejection ratio (CMRR). The proposed circuit was designed and simulated using complementary bipolar process. The simulation results showed that the output voltage range remains constant regardless of the input common-mode voltages, the CMRR is greater than 150 dB, and the Gain Bandwidth Product (GBW) was 4.1 MHz. The advantages of the proposed ICMR-enhanced three-opamp IA will enable its use in more environments.</div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S1879239124000468/pdfft?md5=5fc710a9fd171c502f7eb7cb0709cd5c&pid=1-s2.0-S1879239124000468-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141849684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0