Junyao Ji , Peiyu Li , Bo Wang , Youxiang Chen , Jie Shao , Xiaojie Fan , Mingyuan Ye , Yan Xue , Yingdan Jiang , Jie Zhang , Ruitao Wang , Xiaofei Wang , Hong Zhang
{"title":"5-GSPS连续时间ΔΣ调制器,嵌套前馈补偿OTA和电阻接地电流转向DAC,实现225-MHz带宽和68.5 db信噪比","authors":"Junyao Ji , Peiyu Li , Bo Wang , Youxiang Chen , Jie Shao , Xiaojie Fan , Mingyuan Ye , Yan Xue , Yingdan Jiang , Jie Zhang , Ruitao Wang , Xiaofei Wang , Hong Zhang","doi":"10.1016/j.mejo.2025.106854","DOIUrl":null,"url":null,"abstract":"<div><div>This paper presents a 5-GSPS, 3rd-order continuous-time (CT) ΔΣ modulator in 28-nm CMOS process for wideband communications, in which operational transconductance amplifiers (OTAs) with nested feedforward compensation (NFC) and resistive-grounded current-steering DAC are proposed to address challenges of nonlinearity and thermal noise. The modulator is designed with a single-loop cascade resonator feedback (CRFB) topology to avoid signal/noise leakage issues in multistage architectures, while reference shuffling and self-timed capacitor-voltage DAC are combined to compensate the excess loop delay (ELD) with immunity to process, voltage and temperature (PVT) variations. A resistive-grounded current-steering DAC is employed in the main feedback path, which reduces thermal noise by about 30 % compared to conventional transistor-based grounding scheme. The OTA with NFC in the integrator adopts negative transconductance with neutralization capacitors to enhance the in-band gain, while an R-2R based programmable resistor structure is also employed for the integrator to realize reconfigurable system coefficients with almost constant input impedance. With a layout area of 0.35 mm<sup>2</sup>, simulation results demonstrate that the CT ΔΣ modulator achieves a 68.5-dB signal-to-noise ratio (SNR), a 76.6-dB spurious-free dynamic range (SFDR), and an 11.1-bit effective number of bits (ENOB) in 225-MHz bandwidth, with 112-mW power consumption and Schreier figure-of-merit (FoMs) of 162.1-dB.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106854"},"PeriodicalIF":1.9000,"publicationDate":"2025-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 5-GSPS continuous-time ΔΣ modulator with nested feedforward compensation OTA and resistive−grounded current-steering DAC achieving 225-MHz bandwidth and 68.5-dB SNR\",\"authors\":\"Junyao Ji , Peiyu Li , Bo Wang , Youxiang Chen , Jie Shao , Xiaojie Fan , Mingyuan Ye , Yan Xue , Yingdan Jiang , Jie Zhang , Ruitao Wang , Xiaofei Wang , Hong Zhang\",\"doi\":\"10.1016/j.mejo.2025.106854\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>This paper presents a 5-GSPS, 3rd-order continuous-time (CT) ΔΣ modulator in 28-nm CMOS process for wideband communications, in which operational transconductance amplifiers (OTAs) with nested feedforward compensation (NFC) and resistive-grounded current-steering DAC are proposed to address challenges of nonlinearity and thermal noise. The modulator is designed with a single-loop cascade resonator feedback (CRFB) topology to avoid signal/noise leakage issues in multistage architectures, while reference shuffling and self-timed capacitor-voltage DAC are combined to compensate the excess loop delay (ELD) with immunity to process, voltage and temperature (PVT) variations. A resistive-grounded current-steering DAC is employed in the main feedback path, which reduces thermal noise by about 30 % compared to conventional transistor-based grounding scheme. The OTA with NFC in the integrator adopts negative transconductance with neutralization capacitors to enhance the in-band gain, while an R-2R based programmable resistor structure is also employed for the integrator to realize reconfigurable system coefficients with almost constant input impedance. With a layout area of 0.35 mm<sup>2</sup>, simulation results demonstrate that the CT ΔΣ modulator achieves a 68.5-dB signal-to-noise ratio (SNR), a 76.6-dB spurious-free dynamic range (SFDR), and an 11.1-bit effective number of bits (ENOB) in 225-MHz bandwidth, with 112-mW power consumption and Schreier figure-of-merit (FoMs) of 162.1-dB.</div></div>\",\"PeriodicalId\":49818,\"journal\":{\"name\":\"Microelectronics Journal\",\"volume\":\"165 \",\"pages\":\"Article 106854\"},\"PeriodicalIF\":1.9000,\"publicationDate\":\"2025-08-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronics Journal\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S1879239125003030\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239125003030","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A 5-GSPS continuous-time ΔΣ modulator with nested feedforward compensation OTA and resistive−grounded current-steering DAC achieving 225-MHz bandwidth and 68.5-dB SNR
This paper presents a 5-GSPS, 3rd-order continuous-time (CT) ΔΣ modulator in 28-nm CMOS process for wideband communications, in which operational transconductance amplifiers (OTAs) with nested feedforward compensation (NFC) and resistive-grounded current-steering DAC are proposed to address challenges of nonlinearity and thermal noise. The modulator is designed with a single-loop cascade resonator feedback (CRFB) topology to avoid signal/noise leakage issues in multistage architectures, while reference shuffling and self-timed capacitor-voltage DAC are combined to compensate the excess loop delay (ELD) with immunity to process, voltage and temperature (PVT) variations. A resistive-grounded current-steering DAC is employed in the main feedback path, which reduces thermal noise by about 30 % compared to conventional transistor-based grounding scheme. The OTA with NFC in the integrator adopts negative transconductance with neutralization capacitors to enhance the in-band gain, while an R-2R based programmable resistor structure is also employed for the integrator to realize reconfigurable system coefficients with almost constant input impedance. With a layout area of 0.35 mm2, simulation results demonstrate that the CT ΔΣ modulator achieves a 68.5-dB signal-to-noise ratio (SNR), a 76.6-dB spurious-free dynamic range (SFDR), and an 11.1-bit effective number of bits (ENOB) in 225-MHz bandwidth, with 112-mW power consumption and Schreier figure-of-merit (FoMs) of 162.1-dB.
期刊介绍:
Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems.
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