Microelectronics Journal最新文献_第6页

A reconfigurable MRAM PUF with high reliability 具有高可靠性的可重构MRAM PUF

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-06-07 DOI: 10.1016/j.mejo.2025.106745

Zesheng Chen , Yuan Zhang , Chaoqun Shen

{"title":"A reconfigurable MRAM PUF with high reliability","authors":"Zesheng Chen , Yuan Zhang , Chaoqun Shen","doi":"10.1016/j.mejo.2025.106745","DOIUrl":"10.1016/j.mejo.2025.106745","url":null,"abstract":"<div><div>Physical unclonable function (PUF) has been increasingly applied in the Internet of Things (IoT) fields due to its high security. With the emergence of novel devices, magnetoresistive random access memory (MRAM)-based PUF technology offers excellent energy efficiency and integration density. However, it falls short in terms of response reliability. To address this issue, in this paper, we propose a high-reliability reconfigurable MRAM PUF. First, we propose a novel reconfigurable PUF cell based on the characteristics of MRAM devices. Then, we introduce a sleep mode to reduce the power consumption of PUF. Moreover, we propose a resistance configuration strategy in conjunction with the configurable features of MRAM, which further enhances reliability without increasing hardware overhead. The design is simulated and tested in the SMIC 40 nm process. Experimental results demonstrate that the proposed PUF has a uniqueness of 50.02% and a uniformity of 49.98%, both of which are close to the ideal values. Finally, the bit error rate (BER) is less than 2.2% under temperatures of −40 <span><math><mo>∼</mo></math></span> 120 °C and voltages of 0.7 <span><math><mo>∼</mo></math></span> 1.4 V, which effectively improves the reliability.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"163 ","pages":"Article 106745"},"PeriodicalIF":1.9,"publicationDate":"2025-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144280879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A background calibration technique for SAR ADCs with split capacitor array 分体电容阵列SAR adc的背景标定技术

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-06-06 DOI: 10.1016/j.mejo.2025.106766

Jiacong Wang , Biyun Du , Zhangjie Su , Hongjian Ren , Wenya Luo , Chengchen Song , Chao Cao , Shubin Liu , Haijun Guo

引用次数: 0

A robust internal reference voltage generation circuit with self-adaptive calibration scheme for receiver in NV-DDR interface 基于NV-DDR接口的接收机鲁棒内部基准电压产生电路及自适应校准方案

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-06-06 DOI: 10.1016/j.mejo.2025.106744

Yongshan Wang , Fei Liu , Fangyuan Jin , Jian Huo

{"title":"A robust internal reference voltage generation circuit with self-adaptive calibration scheme for receiver in NV-DDR interface","authors":"Yongshan Wang , Fei Liu , Fangyuan Jin , Jian Huo","doi":"10.1016/j.mejo.2025.106744","DOIUrl":"10.1016/j.mejo.2025.106744","url":null,"abstract":"<div><div>This paper models and analyzes the impacts of impedance mismatch and synchronous switch noise (SSN) on data IO signals in NV-DDR interface. Based on the model, a robust internal reference voltage calibration scheme is proposed. This scheme utilizes a low-pass filter to extract the mid level of data eye diagram from the clock pattern data. According to the above level, a self-adaptive calibration loop based on successive approximation search (SAR) algorithm is adopted to quickly generate the internal reference voltage, thus ensuring the reliability of internal reference voltage. The proposed internal reference voltage generation circuit can reduce the interference of impedance mismatch and SSN, and adaptively generate the internal reference voltage in different interface modes. The test chip is fabricated in 180 nm CMOS process and the area occupies 0.0418 mm<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span>. The measurement results indicate that the internal reference voltage calibration error is within <span><math><mrow><mn>0</mn><mo>.</mo><mn>5</mn><mtext>%</mtext><mi>⋅</mi><mi>V</mi><mi>c</mi><mi>c</mi><mi>Q</mi></mrow></math></span> under diverse IO signals ranging from 800 MT/s to 2400 MT/s.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"163 ","pages":"Article 106744"},"PeriodicalIF":1.9,"publicationDate":"2025-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144264082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High-selectivity wideband bandpass filter with tunable notched band 带可调陷波带的高选择性宽带带通滤波器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-06-03 DOI: 10.1016/j.mejo.2025.106752

Litian Wang , Tengfei Du , Xiaohan Wan , Shanfeng Sun , Mengmeng Cui , Jianyu Ren , Yuqi Li , Lirong Qian , Cuiping Li , Honglang Li , Dan Li , Yang Xiong , Weipeng Xiong , Xiaokun Bi

引用次数: 0

An interval-adaptive correlated multiple sampling ADC with prejudgment logic for low-noise CMOS image sensors 用于低噪声CMOS图像传感器的带预判逻辑的间隔自适应相关多采样ADC

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-06-03 DOI: 10.1016/j.mejo.2025.106720

Qiang Zhao , Shiqi Dang , Zhendong Niu , Bin Qiang , Chunhui Fan , Zhigang Li , Licai Hao , Chunyu Peng , Zhiting Lin , Xiulong Wu

{"title":"An interval-adaptive correlated multiple sampling ADC with prejudgment logic for low-noise CMOS image sensors","authors":"Qiang Zhao , Shiqi Dang , Zhendong Niu , Bin Qiang , Chunhui Fan , Zhigang Li , Licai Hao , Chunyu Peng , Zhiting Lin , Xiulong Wu","doi":"10.1016/j.mejo.2025.106720","DOIUrl":"10.1016/j.mejo.2025.106720","url":null,"abstract":"<div><div>The use of correlated multiple sampling(CMS) in CMOS image sensor(CIS) can significantly reduce the noise in readout circuits, but employing CMS leads to an increase in the conversion time and power consumption of ADC. This paper presents an interval-adaptive correlated multiple sampling ADC with prejudgment logic for low-noise CMOS image sensors. This ADC first uses a 6-bit SAR ADC to perform coarse conversion in order to choose a small-range interval, and then permits the 6-bit fine conversion to be performed only in this interval. In addition, to further reduce power consumption, prejudgment logic is used to eliminate the coarse conversion process by taking advantage of the nature of the similarity of neighboring pixel values in CIS and the structure of SAR ADC that are shared by two columns. The proposed ADC is fabricated using a 130 nm CIS process. The simulation results show that the ADC has a differential nonlinearity (DNL) of -0.75/+1 LSB, an integral nonlinearity (INL) of -1.2/+0.5 LSB, and an input referred noise of 122.5 <span><math><mi>μ</mi></math></span>Vrms , achieving a conversion time of <span><math><mrow><mn>4</mn><mo>.</mo><mn>1</mn><mspace></mspace><mi>μ</mi><mi>s</mi></mrow></math></span> in bright condition, <span><math><mrow><mn>6</mn><mo>.</mo><mn>5</mn><mspace></mspace><mi>μ</mi><mi>s</mi></mrow></math></span> in dark conditions, and the up to 20.3 % reduction in column power consumption relative to traditional CMS ADC without prejudgement logic.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"163 ","pages":"Article 106720"},"PeriodicalIF":1.9,"publicationDate":"2025-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144204898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A high power supply rejection LDO with ripple neutralization technique for Sigma-Delta D/A converter 一种用于Sigma-Delta D/A转换器的高电源抑制LDO及纹波中和技术

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-29 DOI: 10.1016/j.mejo.2025.106746

Xingyuan Tong, Zongxiang Liu, Yinbo Li, Xin Xin

引用次数: 0

Crystal plasticity finite element simulation of TSV microstructure under thermal and vibration loading 热和振动载荷下TSV显微组织的晶体塑性有限元模拟

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-29 DOI: 10.1016/j.mejo.2025.106757

Guifang Chen , Xin You , Yeting Xu , Hongjiang Qian , Peng Wang

{"title":"Crystal plasticity finite element simulation of TSV microstructure under thermal and vibration loading","authors":"Guifang Chen , Xin You , Yeting Xu , Hongjiang Qian , Peng Wang","doi":"10.1016/j.mejo.2025.106757","DOIUrl":"10.1016/j.mejo.2025.106757","url":null,"abstract":"<div><div>The reliability of through-silicon-via (TSV) microstructures for advanced packaging is crucial. Few studies address their micro-mechanical behavior under thermal cycling, vibration, and thermal-vibration coupled loading. This study uses crystal plasticity finite element method (CPFEM) to investigate plastic deformation in TSVs. Plastic work (<em>W</em><sub><em>p</em></sub>) is used as a fatigue indicator parameter (FIP) for crack initiation prediction. CPFEM simulations show thermo-mechanical coupling causes the highest <em>W</em><sub><em>p</em></sub> amplitude, reducing fatigue life in the low-cycle fatigue (LCF) regime. Vibration loading mainly leads to high-cycle fatigue (HCF) or very high-cycle fatigue (VHCF). Crack initiation patterns vary: thermal cycling and thermo-mechanical coupling cause multi-site nucleation in TSV-Cu and at interfaces, while vibration loading results in single-point initiation at interfaces. Microstructural analysis reveals thermal cycling activates slip systems at quadruple-junction grain boundaries (GBs), with stress concentrations between clustered soft grains surrounded by hard phases. Thermo-mechanical coupling initiates cracks at trident GBs due to hard grain extrusion from yielding soft phases. Interface crack locations under hybrid loading relate to the distribution of the hardest grain. These results highlight the importance of loading type and microstructure in TSV degradation, emphasizing the need for grain boundary engineering and dimensional optimization to mitigate thermo-mechanical fatigue.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"162 ","pages":"Article 106757"},"PeriodicalIF":1.9,"publicationDate":"2025-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144189874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A valley-sensed emulated peak current-mode controlled buck converter for dual-channel DDR memory systems 一种用于双通道DDR存储系统的谷感模拟峰值电流模式控制降压变换器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-29 DOI: 10.1016/j.mejo.2025.106730

Xiaopeng Diao , Zhiyong Zhu , Kaifei Fang , Hao Wen , Lishuang Lin , Ping Li , Hua Fan , Qi Wei , Quanyuan Feng

{"title":"A valley-sensed emulated peak current-mode controlled buck converter for dual-channel DDR memory systems","authors":"Xiaopeng Diao , Zhiyong Zhu , Kaifei Fang , Hao Wen , Lishuang Lin , Ping Li , Hua Fan , Qi Wei , Quanyuan Feng","doi":"10.1016/j.mejo.2025.106730","DOIUrl":"10.1016/j.mejo.2025.106730","url":null,"abstract":"<div><div>This work presents a valley-sensed emulated peak current-mode controlled buck converter specifically optimized for high-performance double data rate synchronous dynamic random access memory (DDR SDRAM) applications. In this work, a dual-channel synchronous buck converter is designed to provide a low voltage required for DDR applications. Building upon traditional emulated peak current-mode control, an innovative circuit structure with configurable pre-bias current sensing is introduced. This enhancement ensures that current sensing components are protected from high voltage stress and prevents sub-harmonic oscillations in the current sensing circuit. More importantly, it enables bidirectional switching of source and sink currents, which is essential for DDR power supply solutions. Experimental verification and testing results demonstrate that the dual-channel buck converter has an input voltage range of 3.3 V to 15 V, with a maximum output sourcing current of 6 A and a peak sinking current of 3 A. The chip is fabricated using 180 nm Bipolar-CMOS-DMOS (BCD) process technology, featuring a minimum turn-on time of 132 ns, a minimum turn-off time of 400 ns, and an operating frequency of 300 kHz. The overall chip dimensions are 2.2 mm <span><math><mo>×</mo></math></span> 3.1 mm, while the core area, excluding pads, measures 1.8 mm <span><math><mo>×</mo></math></span> 2.7 mm.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"162 ","pages":"Article 106730"},"PeriodicalIF":1.9,"publicationDate":"2025-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144203126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel minimized millimeter-wave on-chip spoof surface plasmon polariton and its applications based on IPD technology 一种新的最小化毫米波片上欺骗表面等离子激元及其基于IPD技术的应用

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-29 DOI: 10.1016/j.mejo.2025.106755

Yuyang Zeng, Yongle Wu, Yuhao Yang, Leidan Pan, Weimin Wang

引用次数: 0

On-chip integrated 0.4 GHz & 2.3 GHz Lamb wave resonators: Electrode structure optimization and flip-transfer fabrication 片上集成0.4 GHz和2.3 GHz Lamb波谐振器：电极结构优化和翻转转移制造

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-27 DOI: 10.1016/j.mejo.2025.106751

Jicong Zhao , Qiner Xu , Shitao Lv , Wenhao Ye , Qiang Xu , Yi Cao , Haiyan Sun , Jing Huang

{"title":"On-chip integrated 0.4 GHz & 2.3 GHz Lamb wave resonators: Electrode structure optimization and flip-transfer fabrication","authors":"Jicong Zhao , Qiner Xu , Shitao Lv , Wenhao Ye , Qiang Xu , Yi Cao , Haiyan Sun , Jing Huang","doi":"10.1016/j.mejo.2025.106751","DOIUrl":"10.1016/j.mejo.2025.106751","url":null,"abstract":"<div><div>—Lamb wave resonators show great potential for applications in RF filters, infrared detectors, and sensors. Converting the bottom electrode into an interdigitated-transducer (IDT) structure allows broader application. However, the piezoelectric film deposited atop patterned IDTs often suffers from poor quality and cracking, degrading or damaging resonator performance. This study presents a wafer-level flip-transfer method which flips the pre-defined piezoelectric vibration and cavity structures onto another wafer. This reversed the sequence of bottom electrode patterning and piezoelectric film deposition, avoiding the problem above. Utilizing this process, Lamb wave resonators operating at 0.4 GHz and 2.3 GHz with both IDT-IDT and IDT-Floating configurations were integrated on an 8-inch wafer. Furthermore, electrode parameters were optimized to enable the multi-mode coupling and suppress spurious signals. Test results indicate that, with 9.5 % Sc doping, Lamb wave resonators operating in the 0.4 GHz and 2.3 GHz bands achieved effective electromechanical coupling coefficients (<em>k</em><sub><em>t</em></sub><sup>2</sup>) of 2.87 % and 6.24 %, and quality factors (<em>Q</em>) of 2547 and 1332, respectively.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"162 ","pages":"Article 106751"},"PeriodicalIF":1.9,"publicationDate":"2025-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144203127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0