Microelectronics Journal最新文献

{"title":"A high CMRR inverter-based amplifier employing turbo-boost CMFB Loop for multi-channel bio-signal recording","authors":"Siyuan Xie ,&nbsp;Longbin Zhu ,&nbsp;Wenjie Wang ,&nbsp;Kaiyi Xu ,&nbsp;Zhijun Zhou ,&nbsp;Keping Wang","doi":"10.1016/j.mejo.2025.106847","DOIUrl":"10.1016/j.mejo.2025.106847","url":null,"abstract":"<div><div>This paper presents a high common mode rejection ratio (CMRR) capacitively coupled inverter-based amplifier (CC-INV) with a turbo-boost common-mode feedback (TB-CMFB) loop for multi-channel bio-signal recording. TB-CMFB consists of boost and turbo system-CMFB cells. The boost cell significantly attenuates the common-mode (CM) output. By further introducing the turbo cell, the CMRR of CC-INVs is much improved without relying on a large capacitance ratio in the CC-INVs or CMFB loops, maintaining high area efficiency. The proposed 4-channel CC-INVs with TB-CMFB loop is designed in a 0.18-<span><math><mi>μ</mi></math></span>m CMOS technology. It dissipates circa 0.9 <span><math><mi>μ</mi></math></span>W from a 1.8 V supply per channel, while occupying an area of 0.024 mm<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span>, and achieves a CMRR of circa 100 dB.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"166 ","pages":"Article 106847"},"PeriodicalIF":1.9,"publicationDate":"2025-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145049655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Attention mechanism based IP design for dynamic channel selection in EEG epilepsy detect","authors":"Ying Wang ,&nbsp;Lixun Wang ,&nbsp;Yuejun Zhang ,&nbsp;Yi Gong ,&nbsp;Hanyu Shi ,&nbsp;Huihong Zhang ,&nbsp;Pengjun Wang","doi":"10.1016/j.mejo.2025.106864","DOIUrl":"10.1016/j.mejo.2025.106864","url":null,"abstract":"<div><div>Epilepsy, a prevalent neurological disorder requiring low-cost rapid detection in wearable devices, prompts this study to propose a channel attention mechanism(CAM) and convolutional neural network(CNN) hybrid framework that mitigates redundant electroencephalogram(EEG) channel interference and enhances cross-patient generalization through dynamic channel selection. The framework uses CAM to dynamically selects high-information EEG channels across patients/timepoints, eliminating redundancy through feature interaction analysis and feeds them into the CNN to carry out the feature extraction and classification.Then, lightweight processing means such as global average pooling(GAP) and dilated convolution are used to reduce the number of neurons and network complexity, and parallelisation means such as bitonic sorting and pulsed arrays are combined to achieve low-latency effects. Moreover, the hardware IP is designed under the 16-bit mixed-precision fixed-point coding and serial-parallel combination architecture. Implemented on TSMC 65nm process, the design achieves 97.1% accuracy with 77% storage reduction, 1.38mm² core area, and 37.28μs latency (5-10× faster than others) at 0.206μJ/class energy efficiency under 1V/20MHz conditions.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106864"},"PeriodicalIF":1.9,"publicationDate":"2025-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145003973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A design of 96 GS/s 7-bit DAC for high-speed wireline transmitter in 28-nm CMOS","authors":"Junfei Deng,&nbsp;Huolian Liu,&nbsp;Chenxi Han,&nbsp;Li Dang,&nbsp;Hongzhi Liang,&nbsp;Shubin Liu","doi":"10.1016/j.mejo.2025.106863","DOIUrl":"10.1016/j.mejo.2025.106863","url":null,"abstract":"<div><div>This paper presents a 96 GS/s 7-bit digital-to-analog converter (DAC) for a 200 Gb/s＋ wireline transmitter. The impact of mismatch of current sources is reduced by introducing a dual segmentation strategy and local dynamic element matching (DEM). An 8:1 multiplexer (MUX) with edge-enhanced 1-UI pulse generator is proposed for high-speed data serialization, simplifying the clock generation circuit. In addition, the influence of the output network on the dynamic performance of the DAC is also analyzed. The proposed DAC prototype is designed based on the 28-nm CMOS process. The post simulation results show that the proposed DAC achieves spurious free dynamic range (SFDR) of 37.20-dB and signal-to-noise and distortion (SNDR) of 30.91-dB at 96 GS/s sampling rate under the nyquist output frequency. For eight level pulse amplitude modulation (PAM-8) encoding, the 288-Gb/s eye diagram demonstrates 78 mV vertical eye opening and 0.253-UI horizontal eye width, achieving 0.52 pJ/bit energy efficiency of DAC core.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"166 ","pages":"Article 106863"},"PeriodicalIF":1.9,"publicationDate":"2025-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145027501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 13 bit 4MS/s SAR ADC with energy-efficient bidirectional delay generation","authors":"Sewon Lee,&nbsp;Hyein Kang,&nbsp;Minjae Lee","doi":"10.1016/j.mejo.2025.106858","DOIUrl":"10.1016/j.mejo.2025.106858","url":null,"abstract":"<div><div>This paper presents a bidirectional delay generation scheme for an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC), achieving both low power consumption and a wide delay range. The proposed inverter-based delay circuit incorporates poly resistors at both supply rails (<span><math><msub><mrow><mtext>V</mtext></mrow><mrow><mtext>DD</mtext></mrow></msub></math></span> and ground), minimizing load capacitance while extending the achievable delay range. Unlike conventional unidirectional charging schemes that require a reset phase, the proposed bidirectional charging and discharging technique reuses stored charge, reducing energy overhead and enabling multiple delay configurations. These modes are dynamically applied within the SAR conversion cycle, ensuring stable CDAC settling and energy-efficient comparator clocking. To validate the proposed scheme, a 13 bit SAR ADC was implemented in a 65-nm LP CMOS process, consuming 59.3 <span><math><mi>μ</mi></math></span>W at 4 MS/s. The bidirectional delay circuit accounts for only 2% of total power, while the comparator clock generator occupies 3% of ADC area, demonstrating minimal overhead. The prototype achieves an SNDR of 73 dB and a Walden figure of merit (FoM<span><math><msub><mrow></mrow><mrow><mtext>W</mtext></mrow></msub></math></span>) of 4.1 fJ/conversion-step, making it competitive with state-of-the-art SAR ADCs requiring nanosecond-level delay generation.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106858"},"PeriodicalIF":1.9,"publicationDate":"2025-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144922453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel background bandwidth calibration technique in a SHA-less dual-channel 14-bit 125 MS/s pipeline ADC","authors":"Wei Zhang ,&nbsp;Zhaojiang Li ,&nbsp;Xizhu Peng ,&nbsp;He Tang","doi":"10.1016/j.mejo.2025.106856","DOIUrl":"10.1016/j.mejo.2025.106856","url":null,"abstract":"<div><div>This paper presents a bandwidth mismatch calibration technique for SHA-less pipeline analog-to-digital converter(ADC). For SHA-less ADC, bandwidth mismatch causes group delay discrepancy, resulting in poor linearity and missing codes, significantly deteriorating the high frequency dynamic performance. To address this, a novel background calibration technique which identifies the group delay discrepancy and effectively compensates it using a programmable delay-line is proposed. To further enhance linearity, a shuffling technique is implemented, effectively redistributing harmonic distortion into the noise floor. A dual-channel SHA-less 14-bit 125 MS/s prototype ADC is fabricated in a 180-nm CMOS process, reaching signal-to-noise and distortion ratio (SNDR) of 72.5 dB and spurious-free dynamic range (SFDR) of 98.9 dB with a 13 MHz input signal, and improves SFDR from 64 dB to 75 dB with a 493 MHz input signal after calibration, effectively mitigating the bandwidth-mismatch induced nonlinearities.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106856"},"PeriodicalIF":1.9,"publicationDate":"2025-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144931974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Machine-learning-assisted EEHEMT compact modeling of GaN HEMTs","authors":"Censong Liu ,&nbsp;Jie Wang ,&nbsp;Shuzhen You ,&nbsp;Dawei Wang ,&nbsp;Zhiping Yu","doi":"10.1016/j.mejo.2025.106861","DOIUrl":"10.1016/j.mejo.2025.106861","url":null,"abstract":"<div><div>We present a machine learning approach that enhances the EEHEMT model for predicting current–voltage (I–V) characteristics of AlGaN/GaN high electron mobility transistors (HEMTs), focusing on the normalized transconductance-to-current characteristic <span><math><mrow><msub><mrow><mi>g</mi></mrow><mrow><mi>m</mi></mrow></msub><mo>/</mo><msub><mrow><mi>I</mi></mrow><mrow><mi>D</mi></mrow></msub></mrow></math></span>. Instead of replacing model equations, an artificial neural network (ANN) is used to predict key parameters governing the EEHEMT model’s piecewise segments, enabling segmentation adaptive to device geometries and bias conditions. To enhance the accuracy and continuity of first-order derivative of drain current (<span><math><mrow><msub><mrow><mi>g</mi></mrow><mrow><mi>x</mi></mrow></msub><mo>=</mo><mi>∂</mi><mi>I</mi><mo>/</mo><mi>∂</mi><msub><mrow><mi>V</mi></mrow><mrow><mi>x</mi></mrow></msub></mrow></math></span>) while maintaining physically reasonable model behavior, we employ a physics-guided hybrid loss function that combines current fitting error, <span><math><msub><mrow><mi>g</mi></mrow><mrow><mi>x</mi></mrow></msub></math></span> fitting error, a smoothness regularization term on <span><math><msub><mrow><mi>g</mi></mrow><mrow><mi>x</mi></mrow></msub></math></span>, and a monotonic constraint on the breakpoints. The ANN-assisted EEHEMT accurately predicts device characteristics and key metrics such as <span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>t</mi><mi>h</mi></mrow></msub></math></span>, <span><math><msub><mrow><mi>R</mi></mrow><mrow><mi>o</mi><mi>n</mi></mrow></msub></math></span>, and <span><math><msub><mrow><mi>I</mi></mrow><mrow><mi>d</mi><mi>m</mi><mi>a</mi><mi>x</mi></mrow></msub></math></span>. This approach mitigates derivative discontinuities in <span><math><msub><mrow><mi>g</mi></mrow><mrow><mi>x</mi></mrow></msub></math></span>, preserves model interpretability, and enhances generalization across device geometries. Notably, it accurately predicts <span><math><mrow><msub><mrow><mi>g</mi></mrow><mrow><mi>m</mi></mrow></msub><mo>/</mo><msub><mrow><mi>I</mi></mrow><mrow><mi>D</mi></mrow></msub></mrow></math></span>, offering valuable insights into GaN HEMT behavior and enabling efficient, design-oriented device optimization.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106861"},"PeriodicalIF":1.9,"publicationDate":"2025-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144922318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 1.5 GS/s 13-bit partial-interleaving pipelined-SAR ADC with 1/gm load and current-biased ring amplifier","authors":"Jingyuan Xu ,&nbsp;Kai Sun ,&nbsp;Xuan Guo ,&nbsp;Wenhao Ren ,&nbsp;Fangyuan Xu ,&nbsp;Hanbo Jia ,&nbsp;Xinyu Liu","doi":"10.1016/j.mejo.2025.106859","DOIUrl":"10.1016/j.mejo.2025.106859","url":null,"abstract":"<div><div>This article presents a 13-bit 1.5-GS/s ring-amp-based pipelined successive-approximation register (SAR) analog-to-digital converter (ADC) that integrates passive residue transfer and partial interleaving architectures. This architecture achieves high speed while preventing the interleaving skew spurs. The proposed ring amplifier (ring-amp) achieves high speed and strong PVT robustness by adopting a <span><math><mrow><mn>1</mn><mo>/</mo><msub><mrow><mi>g</mi></mrow><mrow><mi>m</mi></mrow></msub></mrow></math></span> load combined with current biasing, which pushes the non-dominant pole to a higher frequency and stabilizes both the gain–bandwidth product (GBW) and phase margin (PM). To verify its performance, the proposed ADC was implemented using a 28-nm CMOS process, and post-layout simulation results show that it achieves an SNDR of 64.35 dB and an SFDR of 82.72 dB near Nyquist input. The ADC consumes 13.25 mW at 1.5 GS/s, achieving a Walden figure of merit (FoM) of 6.55 fJ/conversion-step.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106859"},"PeriodicalIF":1.9,"publicationDate":"2025-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144920181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A two-step single-slope ADC for infrared focal plane array readout circuits","authors":"Jun Liu ,&nbsp;Shunlong He ,&nbsp;Lintong Zhao ,&nbsp;Wei Zou ,&nbsp;Jialong Li ,&nbsp;Longcheng Que ,&nbsp;Yun Zhou ,&nbsp;Jian Lv","doi":"10.1016/j.mejo.2025.106862","DOIUrl":"10.1016/j.mejo.2025.106862","url":null,"abstract":"<div><div>This paper presents a low-power, low-noise, two-step single-slope ADC with low differential nonlinearity (DNL), suitable for large array, high-frame-rate infrared focal plane readout circuits. The proposed two-step single-slope ADC employs a coarse-fine quantization method with continuous ramp and continuous-time comparators. Compared to traditional DAC-based discrete-step ramp and discrete-time comparator schemes, it exhibits lower DNL, reduced dynamic power consumption, and smaller kickback noise. By clock-synchronizing the comparator output signals using D flip-flops, systematic offsets and delay mismatches are eliminated, further reducing integral nonlinearity (INL). To further enhance DNL performance, a simple calibration algorithm based on the redundancy of the coarse-fine quantization section is proposed to optimize the weight ratio between the coarse and fine quantization levels. The proposed column-level ADC is designed in a 0.18 μm CMOS process with an 8 μm column width, achieving a static power consumption of 60 μW per column. Experimental results show that the DNL is less than 0.19 LSB, and the RMS noise is below 150 μV.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106862"},"PeriodicalIF":1.9,"publicationDate":"2025-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144931973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis of 4H-SiC semi-superjunction structures for low switching losses and fast reverse recovery trench MOS with narrow trench gates and integrated MPS diodes","authors":"Mingyang Chen,&nbsp;Quanyuan Feng,&nbsp;Quanyi Zhang,&nbsp;Xiaopei Chen,&nbsp;Yuanchang Zhan","doi":"10.1016/j.mejo.2025.106853","DOIUrl":"10.1016/j.mejo.2025.106853","url":null,"abstract":"<div><div>To concurrently optimize conduction losses, switching characteristics, and breakdown robustness in SiC power MOSFETs, this work introduces a MPS-SSJ-NTGMOS structure combining semi-superjunction, narrow trench gates, and merged PN Schottky (MPS) diode. The semi-superjunction charge compensation increases drift region doping, achieving a specific on-resistance (R_on,sp) of 4.818 mΩ cm² (50.4 % lower than conventional devices). Narrow trench gates reconfigure electrode coupling paths, reducing gate-drain capacitance (C_gd) by 39.4 % and gate charge (Q_g) by 46.5 %, while improving the C_gd figure of merit by 32.48 %, thus enhancing switching speed and reducing losses. The monolithically integrated MPS diode enables conduction primarily through Schottky paths, reducing reverse recovery charge by 38.5 % with a 0.7 V turn-on voltage. Breakdown voltage increases by 33 %–1634 V, with breakdown voltage FOM (BV-FOM) improved by 69.68 %. Compared to conventional superjunction designs, MPS-SSJ-NTGMOS achieves 50.4 % lower conduction losses and 38.3 % lower switching losses under identical conditions, while demonstrating improved dynamic response.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106853"},"PeriodicalIF":1.9,"publicationDate":"2025-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144988542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An energy-efficient data-reused on-the-fly Im2col for OS-dataflow systolic array-based accelerator","authors":"Jianghui Wu,&nbsp;Jianpeng Fan,&nbsp;Xueying Wang,&nbsp;Jun Chen,&nbsp;Weixing Li","doi":"10.1016/j.mejo.2025.106831","DOIUrl":"10.1016/j.mejo.2025.106831","url":null,"abstract":"<div><div>The rapid development of AI technology has made the systolic array, capable of massively parallel computations, one of the most commonly used computational architectures for AI inference. The im2col transformation is required to convert the operation into matrix multiplication for convolution, resulting in inflated input data and increased power consumption for data transmission. This work proposes a low-power, on-the-fly im2col scheme based on data reuse. By delaying or preloading certain input rows, redundant data can be aligned in timing, eliminating the need for extensive intermediate buffers in the im2col module. Additionally, this paper discusses the design of the systolic array for irregular input dataflow and provides hardware support for 1 <span><math><mo>×</mo></math></span> 1 and 3 <span><math><mo>×</mo></math></span> 3 convolution modes. The proposed design has been tested and implemented on the ZYNQ UltraScale+ ZU4EV. Experiment results show that the hardware implementation of the im2col module consumes only 610 LUTs and 465 FFs, with a power consumption of just 6.51 mW, demonstrating better power consumption than previous works.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106831"},"PeriodicalIF":1.9,"publicationDate":"2025-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144908303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}