发布求助
文献互助 智能选刊 最新文献

Microelectronics Journal最新文献

筛选
英文 中文
A novel gate over source-channel overlap dual-gate TFET with insulator pocket and lateral source contact for optimizing subthreshold characteristic 一种新型栅源沟道重叠双栅 TFET，具有绝缘体袋和横向源极触点，可优化阈下特性
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-08-03 DOI: 10.1016/j.mejo.2024.106356
{"title":"A novel gate over source-channel overlap dual-gate TFET with insulator pocket and lateral source contact for optimizing subthreshold characteristic","authors":"","doi":"10.1016/j.mejo.2024.106356","DOIUrl":"10.1016/j.mejo.2024.106356","url":null,"abstract":"<div><p>In this work, we propose a novel hetero-junction hetero-gate-dielectric gate over source-channel overlap dual-gate TFET with an insulator pocket and a lateral source contact (IP-LSC-HJ-HGD-GoSo-DGTFET). In the IP-LSC-HJ-HGD-GoSo-DGTFET, an insulator pocket placed between channel and the right side of source is adopted to suppress the source corner effect which can cause SS to deteriorate. Therefore, an ultra-steep SS<sub>AVER</sub> of 5.5 mV/dec is obtained within 10 orders of magnitude of I<sub>DS</sub>. Moreover, I<sub>OFF</sub> is improved by one order of magnitude when the vertical source contact is replaced by a lateral source contact. Finally, the I<sub>ON</sub>, I<sub>ON</sub>/I<sub>OFF</sub>, V<sub>ONSET</sub>, and g<sub>m</sub> of IP-LSC-HJ-HGD-GoSo-DGTFET are 97 μA/μm, 2.8 × 10<sup>13</sup>, 0 V and 510 μS/μm through the optimization of DC performance, respectively. As for the analog/RF performance, IP-LSC-HJ-HGD-GoSo-DGTFET achieves ƒ<sub>T</sub> of 39 GHz and GBP of 17.3 GHz, respectively. Compared with other GoSo-DGTFETs, the proposed IP-LSC-HJ-HGD-GoSo-DGTFET is a better potential candidate in the application field of ultra-low power integrated circuit.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141961142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A fast-switching and ultra low-loss snapback-free reverse-conducting SOI-LIGBT with Adjustable Carrier Technology 采用可调载流子技术的快速开关超低损耗无反向回扣 SOI-LIGBT
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-08-03 DOI: 10.1016/j.mejo.2024.106358
{"title":"A fast-switching and ultra low-loss snapback-free reverse-conducting SOI-LIGBT with Adjustable Carrier Technology","authors":"","doi":"10.1016/j.mejo.2024.106358","DOIUrl":"10.1016/j.mejo.2024.106358","url":null,"abstract":"<div><p>A snapback-free Reverse-Conduction Silicon On Insulator Lateral Insulate Gate Bipolar Transistor (RC SOI-LIGBT) with Adjustable Carrier Technology (ACT LIGBT) is proposed in this paper. ACT LIGBT adds Semi-Insulating Polycrystalline Silicon (SIPOS) material on the extended gate dielectric, and introduces the potential of the surface SIPOS into the P-type drift region (P-Drift) through SiO<sub>2</sub> trenches. ACT LIGBT generates the inversion layer of electrons in the P-Drift due to the linear potential distribution brought by the high resistance characteristic of SIPOS, resulting in the adjustment of the number of electrons and holes, and forming the technology of ACT. Additionally, ACT LIGBT adds a hole extraction path during it turned off. Meanwhile, compared to SSA LIGBT, ACT LIGBT optimized the <em>BV</em> (700V) by 34 %, while also optimizing the <em>V</em><sub>on</sub> (1.69V) by 25 %, turn-off time (<em>t</em><sub>off</sub> = 12ns) by 92 %, turn-off loss (<em>E</em><sub>off</sub> = 0.69 mJ/cm<sup>2</sup>) by 79 %, and reverse recovery charge (<em>Q</em><sub>rr</sub> = 32.98 μC/cm<sup>2</sup>) by 32.5 %, ultimately achieving a better compromise relationship among <em>BV</em>, <em>V</em><sub>on</sub>, <em>t</em><sub>off</sub>, <em>E</em><sub>off</sub>, and <em>Q</em><sub>rr</sub>.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141961141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Self-clamped P-shield 4H-SiC trench MOSFET for low turn-off loss and suppress switching oscillation 自夹式 P 屏蔽 4H-SiC 沟槽 MOSFET，可降低关断损耗并抑制开关振荡
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-08-02 DOI: 10.1016/j.mejo.2024.106307
{"title":"Self-clamped P-shield 4H-SiC trench MOSFET for low turn-off loss and suppress switching oscillation","authors":"","doi":"10.1016/j.mejo.2024.106307","DOIUrl":"10.1016/j.mejo.2024.106307","url":null,"abstract":"<div><p>A novel 4H-SiC trench MOSFET with self-clamped P-region (SCP-MOS) is proposed. The breakdown voltage is boosted and switching oscillation is suppressed by introducing a lightly P-type doping concentration region (LP) and additional NCSL. P+ and NCSL form a new electric field modulation region that reduces the electric field at the bottom of the gate, resulting in a higher breakdown voltage for the device. Moreover, When <em>V</em><sub>DS</sub> is small, the LP region links P-shield and P+ source region, the P-shield is clamped at a low potential, which effectively reduces the gate to drain capacitance (<em>C</em><sub>GD</sub>). As <em>V</em><sub>DS</sub> increases, the LP region is gradually depleted, causing the P-shield to transition into floating state, the potential in the P-shield region is raised. Consequently, the described characteristics facilitate achieving low turn-off losses and Surge voltage(<em>V</em><sub>Surge</sub>). SCP-MOS has 32 % lower surge voltage compared to GP-MOS and 85 % lower turn-off loss compared to FP-MOS. Overall, SCP-MOS can obtain better <em>E</em><sub>OFF</sub>-<em>V</em><sub>Surge</sub> trade-off.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141961140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low-high-low doped Ga2O3 Schottky barrier IMPATT diodes on various crystal orientations for terahertz applications 用于太赫兹应用的各种晶体取向的低-高-低掺杂 Ga2O3 肖特基势垒 IMPATT 二极管
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-08-02 DOI: 10.1016/j.mejo.2024.106350
{"title":"Low-high-low doped Ga2O3 Schottky barrier IMPATT diodes on various crystal orientations for terahertz applications","authors":"","doi":"10.1016/j.mejo.2024.106350","DOIUrl":"10.1016/j.mejo.2024.106350","url":null,"abstract":"<div><p>This article investigates low-high-low doped Ga<sub>2</sub>O<sub>3</sub> Schottky barrier IMPATT diodes based on [100], [010], and [001] crystal orientations to promote oscillation power at the low-frequency band of terahertz regime. Simulation results demonstrate a conversion power of 4.88 MW/cm<sup>2</sup> along [100] at its optimum frequency of 100 GHz, increasing by 0.73 times and 2.2 times compared to the [100] at 150 GHz and the [001] at 100 GHz, and exhibit the highest conversion efficiency of 6.83 % along [010] as indicated by the DC-RF conversion ability promoting 37 % and 30 % than that of [100] and [001] orientations, respectively. When considering a parasitic resistance of 1 × 10<sup>−5</sup> Ω cm<sup>2</sup>, the optimal frequencies of along three orientations decrease to 90 GHz, 127 GHz, and 91 GHz, correspondingly, yielding the peak output power and total efficiency decrease by 0.3–0.4 times compared to those of the conversion characteristics.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141962537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An all-digital low-complexity blind background calibration of timing mismatch in time-interleaved ADCs 时间交错 ADC 时序失配的全数字低复杂度盲背景校准
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-08-02 DOI: 10.1016/j.mejo.2024.106357
{"title":"An all-digital low-complexity blind background calibration of timing mismatch in time-interleaved ADCs","authors":"","doi":"10.1016/j.mejo.2024.106357","DOIUrl":"10.1016/j.mejo.2024.106357","url":null,"abstract":"<div><p>This paper proposed a novel all-digital blind background calibration to mitigate timing mismatch in time-interleaved analog-to-digital converter (TIADC). In estimation module, the adoption of a subtraction-based error extraction function and the design of Variable-Step-Size Least Mean Squares algorithm contribute to reducing the computational complexity and enhancing the convergence speed with optimal output accuracy respectively. In compensation module, a dual-stage Taylor series expansion structure has been introduced to effectively maintain the overall output performance. The proposed architecture is applied to a 12-bit 3 GS/s four-channel TIADC model. Its effectiveness for single-tone and multi-tone signals is proven through systematical testing and analysis. The simulation results exhibit that the Spurious Free Dynamic Range is significantly improved by 54.53 dB in the single-tone signal case, and the timing mismatch is converged after 1000 samples. The proposed calibration circuit has been synthesized utilizing a 28 nm standard cell library for assessing its hardware consumption, area (0.051 mm<sup>2</sup>) and average power dissipation (67.5 mW) within the integrated chip architecture. Our technology provides a viable optimization solution to improve efficiency of TIADC in high-speed systems.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141962536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2nd-order noise-shaping SAR-assisted pipeline ADC with order-boosted gain-error-shaping 具有阶次增强增益误差整形功能的二阶噪声整形 SAR 辅助流水线 ADC
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-07-31 DOI: 10.1016/j.mejo.2024.106353
{"title":"A 2nd-order noise-shaping SAR-assisted pipeline ADC with order-boosted gain-error-shaping","authors":"","doi":"10.1016/j.mejo.2024.106353","DOIUrl":"10.1016/j.mejo.2024.106353","url":null,"abstract":"<div><p>This paper presents a 4th-order interstage gain error shaping (GES) technique in pipeline successive approximation register (SAR) analog-to-digital converters (ADCs), which can substantially suppress the in-band quantization leakage error induced by the gain error. It is realized by simply arranging a low-order cascaded-integrator feed-forward (CIFF) structure in the first stage. In addition, the comparator noise and quantization error can be shaped together with the gain error in the proposed architecture. Verified by simulation in a 28-nm CMOS process, the prototype achieves a signal-to-noise-and-distortion ratio (SNDR) of 77.8 dB over 25-MHz bandwidth (BW) with oversampling ratio (OSR) of 8. Within a gain error range of −33 % to +33 %, the SNDR of the ADC deviates less than 3 dB. Under a 1 V supply voltage, the ADC consumes 3.75 mW and exhibits a Scherier figure of merit (FoMs) of 176 dB.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141963226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A foreground calibration technique with multi-level dither for a 14-bit 1-MS/s SAR ADC 针对 14 位 1-MS/s SAR ADC 的多级抖动前景校准技术
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-07-26 DOI: 10.1016/j.mejo.2024.106351
{"title":"A foreground calibration technique with multi-level dither for a 14-bit 1-MS/s SAR ADC","authors":"","doi":"10.1016/j.mejo.2024.106351","DOIUrl":"10.1016/j.mejo.2024.106351","url":null,"abstract":"<div><p>A foreground calibration is proposed to obtain the real weights in the split capacitor digital-to-analog- converter (CDAC) of a 14-bit 1-MS/s successive-approximation-register (SAR) ADC. Since the non-linearity of high-resolution SAR ADC is mainly caused by the mismatch of capacitors, calibration of weights of more significant bits is necessary when the resolution of SAR ADC comes to more than 12 bits. By injecting a multi-level dither signal in both the calibration and conversion phases of the calibration scheme, the precision and non-linearity of SAR ADC can be significantly improved. Simulation results indicate that the peak signal-to-noise-and-distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) achieve 79.93 dB and 91.21 dB by employing the proposed calibration technique in a 14-bit split-CDAC SAR ADC. Besides, integral non-linearity (INL) achieves 0.22 least-significant bit (LSB).</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141850473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 3.0-V 4.2-μA 2.23-ppm/°C BGR with cross-connected NPNs and base-current compensation A 3.0-V 4.2-μA 2.23-ppm/°C BGR，带交叉连接的 NPN 和基极电流补偿功能
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-07-25 DOI: 10.1016/j.mejo.2024.106354
{"title":"A 3.0-V 4.2-μA 2.23-ppm/°C BGR with cross-connected NPNs and base-current compensation","authors":"","doi":"10.1016/j.mejo.2024.106354","DOIUrl":"10.1016/j.mejo.2024.106354","url":null,"abstract":"<div><p>This paper presents a high-precision, low-power bandgap voltage reference with a 3.0 V output voltage suitable for battery-management systems. Compared to Brokaw's type bandgap references (BGRs), Cross-connected NPN transistors facilitate higher output voltages without the necessity of operational amplifiers and are unaffected by the current-mirror mismatch. Base-current compensation is proposed to address the effect of base current on voltage output temperature characteristics at low power consumption. A piecewise exponential curvature correction stains high-order compensation for the nonlinear characteristic of base-emitter voltage. Experimental results of the proposed BGR implemented in a 0.18-μm Bipolar-CMOS-DMOS (BCD) process demonstrate that the temperature coefficient is 2.23 ppm/°C over the range of −40 °C–120 °C. The line regulation is 0.2 mV/V at a 5–6 V supply voltage with a supply current of only 4.2 μA. The die area of the fabricated BGR is 0.105 mm<sup>2</sup>.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141850788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A power-efficient fast-transient OCL-LDO with adaptive super source follower and active capacitor compensation management 具有自适应超级源跟随器和有源电容补偿管理功能的高能效快速瞬态 OCL-LDO
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-07-25 DOI: 10.1016/j.mejo.2024.106349
{"title":"A power-efficient fast-transient OCL-LDO with adaptive super source follower and active capacitor compensation management","authors":"","doi":"10.1016/j.mejo.2024.106349","DOIUrl":"10.1016/j.mejo.2024.106349","url":null,"abstract":"<div><p>This paper presents a flipped voltage follower (FVF) based output-capacitor-less low-dropout regulator (OCL-LDO) with fast transient response, high power supply rejection (PSR), and low quiescent current for noise-sensitive circuits in internet-of-things (IoTs). An adaptive super source follower (ASSF) is proposed to effectively reduce the output impedance of the voltage buffer under heavy-loading conditions while keeping a low quiescent current under light-loading conditions. The active capacitor compensation management (ACCM) is proposed to solve the charge-sharing problem caused by the floating capacitors in the dynamic capacitor compensation circuit. The proposed OCL-LDO has been designed and fabricated in 22-nm CMOS technology. It can stabilize with load current ranging from 0 to 12 mA while consuming only 4.8-μA quiescent current. when the load current steps from 0.1 to 10 mA within 3.8 ns, the measured voltage undershoot is 55 mV and the recovery time is about 60 ns.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141843350","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Novel accurate steady-state thermal resistance model for power chips embedded in TTSVs heat dissipation array 嵌入 TTSV 散热阵列的功率芯片的新型精确稳态热阻模型
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-07-25 DOI: 10.1016/j.mejo.2024.106336
{"title":"Novel accurate steady-state thermal resistance model for power chips embedded in TTSVs heat dissipation array","authors":"","doi":"10.1016/j.mejo.2024.106336","DOIUrl":"10.1016/j.mejo.2024.106336","url":null,"abstract":"<div><p>a novel oblique pyramid equivalent heat dissipation model is proposed for theoretically analyzing heat dissipation capacity of power chips with embedded TTSVs. Extra carefully researching correction of oblique thermal resistance, additional lateral thermal resistance, and thermal resistance of TSV insulation sleeve, the accurate theoretical thermal resistance model was established. Setting the FEA simulating results based on <em>COMSOL Multiphysics</em> as benchmark, heat dissipation effects of variation of radius of TTSV (<em>r</em>), thickness of the power chip (<em>H</em><sub>0</sub>), and side length of the single cell (<em>L</em><sub>0</sub>) have been numerically investigated. The maximum temperature relative error of the proposed model with FEA simulated results is not more than 0.2 %, 1 %, and 0.5 % for variation of <em>r</em>, <em>H</em><sub>0</sub>, and <em>L</em><sub>0</sub>, respectively. The proposed model has been theoretically and numerically proven to be effective and accurate.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"141844238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信