Microelectronics Journal最新文献

{"title":"Bandwidth optimization for GaN HEMT terahertz detectors using the advanced SPICE model","authors":"Chaoyu Zhang,&nbsp;Xiaolong Hu","doi":"10.1016/j.mejo.2025.106600","DOIUrl":"10.1016/j.mejo.2025.106600","url":null,"abstract":"<div><div>This paper presents a solution to address the problems for AlGaN/GaN HEMT terahertz detectors. An ASM GaN HEMT model is first developed and validated for the GaN HEMT terahertz detectors using ICCAP simulation. Then, a common-source amplification mode GaN HEMT amplifier with a large impedance is selected for integration with the detector, which offers a higher input impedance and thereby facilitates a better impedance match with the detector. An optimal bandwidth of 212.1 MHz was obtained when the gate voltage of the IF amplifier is at −1.8 V. Finally, the circuit matching is optimized between the GaN HEMT detector and the IF amplifier, and the bandwidth of the integrated chip reaches 626.0 MHz, representing an increase of about 195 % compared to the configuration without circuit matching.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106600"},"PeriodicalIF":1.9,"publicationDate":"2025-02-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143509027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 16-bit 20KSPS SAR ADC with digital background calibration in 0.18 μm CMOS","authors":"Xiaoyuan Miao,&nbsp;Yuhua Liang","doi":"10.1016/j.mejo.2025.106610","DOIUrl":"10.1016/j.mejo.2025.106610","url":null,"abstract":"<div><div>For intelligent Internet of Things applications (IoT) in sustainable agriculture and food industries, after sensors gather environmental data, the quantization process demands low bandwidth and high-precision ADCs. This article presents a 16-bit successive-approximation register (SAR) analog-to-digital converters (ADCs) with a background digital calibration based on Dither and LMS. The proposed SAR ADC is demonstrated through sequential modeling in MATLAB, pre-layout, and post-layout. Designed in a 0.18 μm process, the post-layout simulation results show that it achieves a peak SNDR of 90.1 dB, and a peak SFDR of 106.7 dB with a 10 kHz bandwidth. The power consumption of this SAR ADC is 176.8 μW under a 5V supply. The Schreier Figure-of Merit (FoM_SNDR) is 167.6 dB. The ADC suits low-speed, high-precision IoT systems in sustainable agriculture and food industries.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106610"},"PeriodicalIF":1.9,"publicationDate":"2025-02-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143453849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability analysis of PoP stacked solder joints under thermal cycling load based on the optimal equivalent model","authors":"Chao Gao ,&nbsp;Chunyue Huang ,&nbsp;Ying Liang ,&nbsp;Gui Wang ,&nbsp;Yongling Chen","doi":"10.1016/j.mejo.2025.106596","DOIUrl":"10.1016/j.mejo.2025.106596","url":null,"abstract":"<div><div>An optimal equivalent model for PoP-stacked solder joints is developed based on the nonlinear load-deformation response. The thermal stress distribution of solder joints in PoP assembly arrays subjected to thermal cycling loads is simulated and analyzed. The thermal fatigue failure modes of critical solder joints in the array are discussed, and the thermal fatigue life of these joints is calculated. Furthermore, the influence of structural parameters on solder joint thermal stress is elucidated. The results indicate that the incorporation of the optimal equivalent model not only improves the efficiency of simulation analysis but also enhances the accuracy of solder joint thermal stress prediction. The solder joints in the lower array of the PoP assembly experience higher thermal stress compared to those in the upper array. Solder joints at the corners of the array exhibit higher thermal stress and are identified as critical components. Cracks initially nucleate at the interface between the solder joint and the copper pad, propagating along the interface and eventually appearing within the solder joint. The thermal fatigue life of critical solder joints in the upper array is 3–4 times longer than that of the critical solder joints in the lower array. The ranking of the influence of specific structural parameters on solder joint thermal stress is as follows: solder joint height &gt; solder joint diameter &gt; PCB thickness &gt; substrate thickness. Thermal stress in solder joints exhibits a negative correlation with solder joint height and diameter, and a positive correlation with PCB and substrate thickness.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106596"},"PeriodicalIF":1.9,"publicationDate":"2025-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143444305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A broadband GaAs receiver MMIC for W-band applications","authors":"Zhenbei Li,&nbsp;Huanhuan Guan,&nbsp;Nan Guo,&nbsp;Jian Zhang,&nbsp;Qiuze Yu","doi":"10.1016/j.mejo.2025.106590","DOIUrl":"10.1016/j.mejo.2025.106590","url":null,"abstract":"<div><div>A broadband, multifunctional W-band receiver MMIC (Monolithic Microwave Integrated Circuit) is presented, designed using 0.1-<span><math><mi>μ</mi></math></span>m GaAs pHEMT (pseudomorphic high-electron-mobility transistor) technology from WIN Semiconductors. This MMIC integrates a sextupler, a quadrature resistive mixer, and a low-noise amplifier (LNA), with the sextupler and LNA individually fabricated and tested to optimize performance. Several technologies were employed to enhance the performance of the receiver MMIC. First, a parallel-line coupler, acting as a high-pass filter, reduces lower-order harmonics in the LO chain. Second, radial stubs are applied to chock DC paths in the LO chain for broadband operation. Third, an on-chip LC low-pass filter is incorporated in the IQ mixer to achieve a broad intermediate frequency (IF) bandwidth while minimizing LO signal leakage to the IF port. Measurement results demonstrate a conversion gain of 7–9.5 dB and a noise figure of 5.1–8 dB across an 85–115 GHz frequency range. Compared to other W-band receivers utilizing III-V semiconductor technologies, this GaAs-based receiver MMIC offers a broader operating bandwidth and a competitive noise figure, all within a compact size of <span><math><mrow><mn>2</mn><mo>.</mo><mn>3</mn><mo>×</mo><mn>2</mn><mspace></mspace><msup><mrow><mi>mm</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span>. These attributes make it highly suitable for various W-band applications, including wireless backhaul, radiometry, and millimeter-wave imaging.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106590"},"PeriodicalIF":1.9,"publicationDate":"2025-02-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143421501","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Narrowband ladder-type MEMS filter based on high-Q thin-film piezoelectric-on-silicon MEMS resonators","authors":"Kewen Zhu ,&nbsp;Yuhao Xiao ,&nbsp;Wen Chen ,&nbsp;Guoqiang Wu","doi":"10.1016/j.mejo.2025.106588","DOIUrl":"10.1016/j.mejo.2025.106588","url":null,"abstract":"<div><div>This article reports a narrowband ladder-type microelectromechanical system (MEMS) filter based on thin-film piezoelectric-on-silicon (TPoS) MEMS resonators with high quality factors (<span><math><mrow><mi>Q</mi><mi>s</mi></mrow></math></span>). The reported second-order ladder-type MEMS filter consists of three single-port TPoS MEMS resonators. Dependencies of the resonator’s <span><math><mi>Q</mi></math></span> and effective electromechanical coupling factor (<span><math><msubsup><mrow><mi>k</mi></mrow><mrow><mi>e</mi><mi>f</mi><mi>f</mi></mrow><mrow><mn>2</mn></mrow></msubsup></math></span>), as well as the filter’s bandwidth on the device thickness of the TPoS MEMS resonators are investigated using finite element method (FEM) analysis. The mechanical <span><math><mi>Q</mi></math></span> of the resonator increases while its <span><math><msubsup><mrow><mi>k</mi></mrow><mrow><mi>e</mi><mi>f</mi><mi>f</mi></mrow><mrow><mn>2</mn></mrow></msubsup></math></span> decreases as the thickness of the silicon device layer become thicker from <span><math><mrow><mn>20</mn><mspace></mspace><mi>μ</mi><mi>m</mi></mrow></math></span> to <span><math><mrow><mn>60</mn><mspace></mspace><mi>μ</mi><mi>m</mi></mrow></math></span>, resulting in a lower insertion loss and narrower bandwidth for the designed filter. Measurement results illustrate that the fabricated TPoS resonator with silicon device layer of <span><math><mrow><mn>60</mn><mspace></mspace><mi>μ</mi><mi>m</mi></mrow></math></span> achieves a high <span><math><mi>Q</mi></math></span> of 50258 and <span><math><msubsup><mrow><mi>k</mi></mrow><mrow><mi>e</mi><mi>f</mi><mi>f</mi></mrow><mrow><mn>2</mn></mrow></msubsup></math></span> of 0.094% at its resonant frequency of 25.9 MHz, which agree well with the FEM simulated values. Thanks to the high <span><math><mi>Q</mi></math></span> and low <span><math><msubsup><mrow><mi>k</mi></mrow><mrow><mi>e</mi><mi>f</mi><mi>f</mi></mrow><mrow><mn>2</mn></mrow></msubsup></math></span> of the TPoS MEMS resonator, the reported ladder-type MEMS filter achieves a narrow percent bandwidth of 0.059%, a low insertion loss of 0.71 dB, and a 20-dB shape factor of 1.33 under proper termination impedance. It provides a promising way for achieving narrowband MEMS filters for channel selection at radio frequency in wireless communications.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"157 ","pages":"Article 106588"},"PeriodicalIF":1.9,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143387116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 112 dB SFDR 16-bit 1MS/s SAR ADC with an improved and robust analog self-calibration","authors":"Zhaojiang Li ,&nbsp;Wei Zhang ,&nbsp;Suming Chen ,&nbsp;Xizhu Peng ,&nbsp;He Tang","doi":"10.1016/j.mejo.2025.106587","DOIUrl":"10.1016/j.mejo.2025.106587","url":null,"abstract":"<div><div>This paper introduces a highly linear 16-bit successive approximation register (SAR) ADC, featuring an improved and robust analog voltage calibration method. The proposed method precisely measures binary capacitor mismatch and redundant capacitor mismatch, enabling accurate compensation of mismatch error during normal operation. Both theoretical analysis and measurement results confirm that the proposed method can significantly improve ADC linearity and spectrum purity. Remarkably, the additional calibration capacitive digital-to-analog converter (CDAC) occupies only 5% of total CDAC area. The design, implemented in a 180-nm CMOS process, achieves an average spuriousfree dynamic range (SFDR) of 112 dB without employing any dynamic element matching (DEM) techniques and a signal-to-noise and distortion ratio (SNDR) of 92.6 dB. This prototype operating 3.3V power supply and 1MS/s sampling rate consumes 4.82 mW and achieves a figure of merit (FOM)s of 172.7 dB.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106587"},"PeriodicalIF":1.9,"publicationDate":"2025-02-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143421502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"An 85.6-dB SNDR 1.5 MHz-BW NS-pipelined SAR ADC employing the gain-error-shaping technique to enhance the ADC linearity","authors":"Wenjie Liang ,&nbsp;Dazheng Chen","doi":"10.1016/j.mejo.2025.106593","DOIUrl":"10.1016/j.mejo.2025.106593","url":null,"abstract":"<div><div>This paper presents a noise-shaping (NS) pipelined SAR ADC. For a pipelined-SAR ADC, Gain-error-shaping (GES) techniques executing its function in the digital domain can calibrate and correct amplifier gains, reducing nonlinearity errors introduced by amplifiers and thereby improving the ADC performance. Thanks to the highly digitized structure of SAR ADC, NS-pipelined SAR ADC based on the GES is a promising research direction.</div><div>In a 0.18 μm CMOS process, the proposed ADC achieves a SNDR of 82.57 dB, with the signal bandwidth and the sampling rate being 1.5 MHz and 25 MHz respectively. It consumes 3.37 mW in total at a 1.8-V supply, resulting in a SNDR-based Schreier figure-of-merit (FoMs) of 179.1 dB. The chip area occupied by the ADC core is 1200μm × 800 μm.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"157 ","pages":"Article 106593"},"PeriodicalIF":1.9,"publicationDate":"2025-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143378430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis and design of high-performance liquid crystal phase shifter based on nanowire filled membrane and spoof surface plasmon polaritons","authors":"Haoyuan Wang ,&nbsp;Fanyi Meng ,&nbsp;Lei Tu ,&nbsp;Rong Liu ,&nbsp;Zijun Zheng ,&nbsp;Yuxin Wang ,&nbsp;Chang Ding ,&nbsp;Ruizhi Liu","doi":"10.1016/j.mejo.2025.106595","DOIUrl":"10.1016/j.mejo.2025.106595","url":null,"abstract":"<div><div>In this paper, the design and analysis methods of Liquid crylstal phase shifter (LCPS) with high performance based on nanowire filled membrane (NaM) and spoof surface plasmon polariton (SSPP) are proposed. The equivalent transmission line model and distributed circuit parameters of a NaM-LCPS are constructed and compared with those of a conventional microstrip line liquid crystal phase shifter (ML-LCPS) to reveal the causes of the high figure of merit (FoM) of the NaM-LCPS. Building upon above analyses, an idea of combination of SSPP and NaM-LCPS is proposed to improve the NaM-LCPS's performance. Simulation results show that the NaM-SSPP-LCPS reaches an outstanding FoM of 123.5°/dB and a per wavelength phase shift of 377.5°/λ0, however, NaM-LCPS only has a FoM of 98.9°/dB and a phase shift of 241°/λ0 per wavelength, which increases by 24.87 % and 56.64 % compared to the NaM-LCPS, respectively, implying higher efficiency and more compact physical size.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106595"},"PeriodicalIF":1.9,"publicationDate":"2025-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143386599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 24-kHz bandwidth 94.8-dB-SNDR discrete-time dynamic zoom ADC with analog-domain combine","authors":"Zhenyu Wang ,&nbsp;Huanlin Xie ,&nbsp;Mingchao Jian ,&nbsp;Mingtao Hu ,&nbsp;Bo Sun ,&nbsp;Chunbing Guo","doi":"10.1016/j.mejo.2025.106594","DOIUrl":"10.1016/j.mejo.2025.106594","url":null,"abstract":"<div><div>This article presents a discrete-time (DT) dynamic zoom ADC with analog-domain combine and fractional over-ranging factor. The output of the successive approximation register (SAR) ADC and the delta-sigma modulator (DSM) are directly combined by charge transfer through the proposed extended-CDAC, without a digital combine module. It effectively simplifies the digital circuits of the proposed zoom ADC, and saves the area and power consumption. Combining in the analog-domain also makes it possible to adopt a fractional over-ranging factor (<em>M</em> &lt; 1), thus reducing the SQNR loss. Fabricated in a 65-nm CMOS process, the prototype ADC occupies only 0.15 mm² core area and achieves 94.8-dB peak SNDR, 96.7-dB DR in 24-kHz bandwidth, while consuming 178.1-μW from a 1.1-V Supply, leading to an SNDR-based FoM_S of 176.1-dB.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106594"},"PeriodicalIF":1.9,"publicationDate":"2025-02-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143421503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A chaotic strong transition effect ring oscillator PUF with effective immunity to modeling attacks","authors":"Jingchang Bian,&nbsp;Xingchen Du,&nbsp;Yingchun Lu,&nbsp;Aibin Yan,&nbsp;Huaguo Liang,&nbsp;Zhengfeng Huang","doi":"10.1016/j.mejo.2025.106592","DOIUrl":"10.1016/j.mejo.2025.106592","url":null,"abstract":"<div><div>Although the rapid development of information technology has brought unprecedented convenience and revolutionary changes to human lifestyles, it has also led to serious privacy and security issues. Massive amounts of sensitive information are exchanged within cyber-physical systems (CPS), and the storage and authentication processes of this information are highly susceptible to the attention of malicious attackers. Strong physical unclonable function (PUF) is a crucial hardware security primitive for identity authentication in lightweight internet of things (IoT) devices. However, most of the existing strong PUFs have failed to resist advanced modeling attacks based on machine learning. The paper proposes a chaotic strong transition effect ring oscillator (CS-TERO) PUF, which combines the nonlinearity of strong TERO and the unpredictability of chaotic design to resist modeling attacks. The strong PUF feature is achieved through configurable dual XOR gates and extended TERO chains. Chaotic operations are performed by obfuscating challenges using logical mapping functions. Experimental results demonstrate that the CS-TERO PUF successfully resists state-of-the-art modeling attacks, and the accuracy of all attacks is below 70 %. Compared to other modeling attack-resilient PUFs, our CS-TERO PUF requires fewer hardware resources, saving almost 25 % of area overhead compared to the most lightweight solutions. Additionally, the CS-TERO PUF demonstrates a reliability of 98.27 %, uniqueness of 53.65 %, and uniformity of 49.26 %, reaching an advanced strong PUF application standard. Furthermore, the randomness has also passed the internationally accredited NIST 800-22 S P test.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"157 ","pages":"Article 106592"},"PeriodicalIF":1.9,"publicationDate":"2025-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143378429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}