A 13 bit 4MS/s SAR ADC with energy-efficient bidirectional delay generation

This paper presents a bidirectional delay generation scheme for an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC), achieving both low power consumption and a wide delay range. The proposed inverter-based delay circuit incorporates poly resistors at both supply rails (${\text{V}}_{\text{DD}}$ and ground), minimizing load capacitance while extending the achievable delay range. Unlike conventional unidirectional charging schemes that require a reset phase, the proposed bidirectional charging and discharging technique reuses stored charge, reducing energy overhead and enabling multiple delay configurations. These modes are dynamically applied within the SAR conversion cycle, ensuring stable CDAC settling and energy-efficient comparator clocking. To validate the proposed scheme, a 13 bit SAR ADC was implemented in a 65-nm LP CMOS process, consuming 59.3 $\mu$W at 4 MS/s. The bidirectional delay circuit accounts for only 2% of total power, while the comparator clock generator occupies 3% of ADC area, demonstrating minimal overhead. The prototype achieves an SNDR of 73 dB and a Walden figure of merit (FoM${}_{\text{W}}$) of 4.1 fJ/conversion-step, making it competitive with state-of-the-art SAR ADCs requiring nanosecond-level delay generation.