A 1.5 GS/s 13-bit partial-interleaving pipelined-SAR ADC with 1/gm load and current-biased ring amplifier

This article presents a 13-bit 1.5-GS/s ring-amp-based pipelined successive-approximation register (SAR) analog-to-digital converter (ADC) that integrates passive residue transfer and partial interleaving architectures. This architecture achieves high speed while preventing the interleaving skew spurs. The proposed ring amplifier (ring-amp) achieves high speed and strong PVT robustness by adopting a $1/g_m$ load combined with current biasing, which pushes the non-dominant pole to a higher frequency and stabilizes both the gain–bandwidth product (GBW) and phase margin (PM). To verify its performance, the proposed ADC was implemented using a 28-nm CMOS process, and post-layout simulation results show that it achieves an SNDR of 64.35 dB and an SFDR of 82.72 dB near Nyquist input. The ADC consumes 13.25 mW at 1.5 GS/s, achieving a Walden figure of merit (FoM) of 6.55 fJ/conversion-step.