A novel background bandwidth calibration technique in a SHA-less dual-channel 14-bit 125 MS/s pipeline ADC

Abstract

This paper presents a bandwidth mismatch calibration technique for SHA-less pipeline analog-to-digital converter(ADC). For SHA-less ADC, bandwidth mismatch causes group delay discrepancy, resulting in poor linearity and missing codes, significantly deteriorating the high frequency dynamic performance. To address this, a novel background calibration technique which identifies the group delay discrepancy and effectively compensates it using a programmable delay-line is proposed. To further enhance linearity, a shuffling technique is implemented, effectively redistributing harmonic distortion into the noise floor. A dual-channel SHA-less 14-bit 125 MS/s prototype ADC is fabricated in a 180-nm CMOS process, reaching signal-to-noise and distortion ratio (SNDR) of 72.5 dB and spurious-free dynamic range (SFDR) of 98.9 dB with a 13 MHz input signal, and improves SFDR from 64 dB to 75 dB with a 493 MHz input signal after calibration, effectively mitigating the bandwidth-mismatch induced nonlinearities.