A design of 96 GS/s 7-bit DAC for high-speed wireline transmitter in 28-nm CMOS

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-09-02 DOI:10.1016/j.mejo.2025.106863

Junfei Deng, Huolian Liu, Chenxi Han, Li Dang, Hongzhi Liang, Shubin Liu

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引用次数: 0

Abstract

This paper presents a 96 GS/s 7-bit digital-to-analog converter (DAC) for a 200 Gb/s＋ wireline transmitter. The impact of mismatch of current sources is reduced by introducing a dual segmentation strategy and local dynamic element matching (DEM). An 8:1 multiplexer (MUX) with edge-enhanced 1-UI pulse generator is proposed for high-speed data serialization, simplifying the clock generation circuit. In addition, the influence of the output network on the dynamic performance of the DAC is also analyzed. The proposed DAC prototype is designed based on the 28-nm CMOS process. The post simulation results show that the proposed DAC achieves spurious free dynamic range (SFDR) of 37.20-dB and signal-to-noise and distortion (SNDR) of 30.91-dB at 96 GS/s sampling rate under the nyquist output frequency. For eight level pulse amplitude modulation (PAM-8) encoding, the 288-Gb/s eye diagram demonstrates 78 mV vertical eye opening and 0.253-UI horizontal eye width, achieving 0.52 pJ/bit energy efficiency of DAC core.

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基于28nm CMOS的高速有线发射机用96gs /s 7位DAC设计

本文介绍了一种用于200gb /s+有线发射机的96gs /s 7位数模转换器（DAC）。通过引入双重分割策略和局部动态元素匹配（DEM），降低了电流源不匹配的影响。提出了一种带边缘增强1 ui脉冲发生器的8:1多路复用器（MUX），用于高速数据串行化，简化了时钟产生电路。此外，还分析了输出网络对DAC动态性能的影响。所提出的DAC原型是基于28纳米CMOS工艺设计的。后置仿真结果表明，在奈奎斯特输出频率下，在96 GS/s采样率下，该DAC的无杂散动态范围（SFDR）为37.20 db，信噪比和失真（SNDR）为30.91 db。对于八电平脉冲幅度调制（PAM-8）编码，288-Gb/s的眼图显示78 mV的垂直眼开度和0.253-UI的水平眼宽，实现了0.52 pJ/bit的DAC核心能量效率。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.