A two-step single-slope ADC for infrared focal plane array readout circuits

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-08-28 DOI:10.1016/j.mejo.2025.106862

Jun Liu , Shunlong He , Lintong Zhao , Wei Zou , Jialong Li , Longcheng Que , Yun Zhou , Jian Lv

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引用次数: 0

Abstract

This paper presents a low-power, low-noise, two-step single-slope ADC with low differential nonlinearity (DNL), suitable for large array, high-frame-rate infrared focal plane readout circuits. The proposed two-step single-slope ADC employs a coarse-fine quantization method with continuous ramp and continuous-time comparators. Compared to traditional DAC-based discrete-step ramp and discrete-time comparator schemes, it exhibits lower DNL, reduced dynamic power consumption, and smaller kickback noise. By clock-synchronizing the comparator output signals using D flip-flops, systematic offsets and delay mismatches are eliminated, further reducing integral nonlinearity (INL). To further enhance DNL performance, a simple calibration algorithm based on the redundancy of the coarse-fine quantization section is proposed to optimize the weight ratio between the coarse and fine quantization levels. The proposed column-level ADC is designed in a 0.18 μm CMOS process with an 8 μm column width, achieving a static power consumption of 60 μW per column. Experimental results show that the DNL is less than 0.19 LSB, and the RMS noise is below 150 μV.

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用于红外焦平面阵列读出电路的两步单斜率ADC

本文提出了一种低功耗、低噪声、低差分非线性（DNL）的两步单斜率ADC，适用于大阵列、高帧率红外焦平面读出电路。所提出的两步单斜率ADC采用粗-细量化方法，采用连续斜坡和连续时间比较器。与传统的基于dac的离散阶跃斜坡和离散时间比较器方案相比，它具有更低的DNL、更低的动态功耗和更小的反扰噪声。通过使用D触发器对比较器输出信号进行时钟同步，消除了系统偏移和延迟不匹配，进一步降低了积分非线性（INL）。为了进一步提高深度神经网络的性能，提出了一种基于粗-细量化部分冗余度的简单标定算法，优化粗-细量化水平的权重比。该柱级ADC采用0.18 μm CMOS工艺设计，柱宽为8 μm，每柱静态功耗为60 μW。实验结果表明，DNL小于0.19 LSB， RMS噪声小于150 μV。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.