A two-step single-slope ADC for infrared focal plane array readout circuits

This paper presents a low-power, low-noise, two-step single-slope ADC with low differential nonlinearity (DNL), suitable for large array, high-frame-rate infrared focal plane readout circuits. The proposed two-step single-slope ADC employs a coarse-fine quantization method with continuous ramp and continuous-time comparators. Compared to traditional DAC-based discrete-step ramp and discrete-time comparator schemes, it exhibits lower DNL, reduced dynamic power consumption, and smaller kickback noise. By clock-synchronizing the comparator output signals using D flip-flops, systematic offsets and delay mismatches are eliminated, further reducing integral nonlinearity (INL). To further enhance DNL performance, a simple calibration algorithm based on the redundancy of the coarse-fine quantization section is proposed to optimize the weight ratio between the coarse and fine quantization levels. The proposed column-level ADC is designed in a 0.18 μm CMOS process with an 8 μm column width, achieving a static power consumption of 60 μW per column. Experimental results show that the DNL is less than 0.19 LSB, and the RMS noise is below 150 μV.