A 0.0013-mm2 7-bit 2-GS/s time-domain 4-bit/cycle SAR ADC with the input-recoverable constant-current VTC

This brief presents a high-speed compact time-domain 4-bit/cycle SAR ADC. The input voltages are converted by an input-recoverable constant-current VTC into a time difference. The time difference is digitized by an enhanced SA-Flash TDC into 4-bit per cycle. Owing to the proposed coupled capacitors in the VTC, which recover the input voltage after conversion, enabling reuse of the same VTC and TDC each SAR cycle to enhance area efficiency. A monotonous CDAC switching scheme is employed to generate voltage residue after the first cycle and accelerates the second voltage-to-time conversion by decreasing the common-mode voltage. Furthermore, the gain of VTC in the second conversion is increased to eight times that of the first conversion by adjusting the discharge current. A single-channel 7-bit 2 GS/s prototype ADC is designed and verified based on 28-nm CMOS. The core layout occupies an area of 0.0013 mm². Post-layout simulations show that SNDR and SFDR are 42.2 dB and 56.4 dB respectively at Nyquist frequency input at TT corner. The ADC consumes 6.7 mW at 0.9 V supply, achieving FoMw of 28.7 fJ/conversion-step and FoMs of 154.8 dB. From 500-point mismatch Monte Carlo simulation, SFDR above 46 dB and SNDR above 38.5 dB without calibration.