Frequency dependence of Clock-SET-induced SEU in DFF

Abstract

Though frequency dependence of static upset in a storage cell and upset caused by single-event transient (SET) in combinational logic between storage cells have been investigated extensively, there is no research on how the upset due to SET on the clock signal changes as the clock frequency increases. Using the Dynamic Dual-Copy Susceptibility Analysis and Evaluation Methodology (DDC-SAEM), the frequency dependence of single event upsets (SEUs) in D-type flip-flop (DFF) caused by SETs occurred in clock inverters or clock buffers is investigated. 80000 and 130000 random electrical simulations were made on the PMOS and NMOS transistors in the clock buffer at the 65 nm and 28 nm process nodes, respectively. Statistical results indicate that, as the clock frequency increases, clock-SET-induced SEU numbers are almost independent on the frequency at first. Then the SEU numbers increases sharply with increasing frequency, and finally the correlation curves converge. The saturation point is around 78% in the 65 nm technology and 88% in the 28 nm technology, respectively. It means that unlike the upset directly generated in the DFF, which remains relatively constant in terms of clock frequency increase and decrease, the probability of SEU induced by SETs on the clock signal is closely related to the clock frequency. When the clock frequency exceeds a certain value, the clock-SET-induced SEU will become very significant. When designing high-performance and high-reliability integrated circuits, it needs to be particularly paid attention to.