一种二阶δ - σ电容-数字转换器，内置误差反馈指数增量噪声整形SAR量化器

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-05-05 DOI:10.1016/j.mejo.2025.106712

Bo Zhao , Yuke Shen , Tao Chen , Yi Shen , Shubin Liu , Ruixue Ding , Zhangming Zhu

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引用次数: 0

摘要

本文提出了一种节能的二阶ΔΣ电容-数字转换器（CDC）。采用一阶误差反馈指数增量噪声整形（EF-EINS）逐次逼近寄存器（SAR）模数转换器（ADC）作为多位量化器。采用电容叠加和动态缓冲技术的EF-EINS SAR量化器提高了电容分辨率。与一阶硬件开销的传统三阶结构相比，它具有优越的量化噪声抑制能力，显著降低了电路复杂性并提高了能效。仿真结果表明，在1.8 V电压下，在5.12 MS/s的工作速率下，该电路的功耗为556.74 μW。在3.125 μs的转换时间内，实现了12.5位的CDC有效位元数（ENOB）和25.32 aF的电容分辨率，显示了0.3 pJ/con .-step的CDC Walden优值（FoMW）。

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A 2nd-order delta-sigma capacitance-to-digital converter with an embedded error-feedback exponential-incremental noise-shaping SAR quantizer

This paper presents an energy-efficient second-order ΔΣ capacitance-to-digital converter (CDC). A first-order error-feedback exponential-incremental noise-shaping (EF-EINS) successive approximation register (SAR) analog-to-digital converter (ADC) is employed as the multi-bit quantizer. The EF-EINS SAR quantizer using capacitor stacking and dynamic buffering techniques is employed to improve the capacitance resolution. It exhibits superior quantization noise suppression capability compared to the conventional third-order structures with a first-order hardware overhead, significantly reducing the circuit complexity and enhancing the energy efficiency. Verified in a 180-nm CMOS process, simulation results show that the proposed CDC consumes 556.74 μW under a 1.8 V supply at a 5.12 MS/s. It achieves a CDC effective number of bits (ENOB) of 12.5 bits and a capacitance resolution of 25.32 aF within a conversion time of 3.125 μs, exhibiting a CDC Walden figure of merit (FoM_W) of 0.3 pJ/conv.-step.

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.