A RISC-V based SoC for blockchain data integration in IoT edge devices

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-04-24 DOI:10.1016/j.mejo.2025.106697

Wentao Xu , Xiang Li , Qiuyan Xu , Yuxuan Zhang , Xiang Wu , Weilin Li , Ruize Wang , Gang Liang , Hao Guo

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引用次数: 0

Abstract

The widespread growth of the Internet of Things (IoT) has significantly increased the need for robust data interaction mechanisms, making data security a critical challenge. Blockchain technology, characterized by its decentralized architecture, presents an innovative solution for managing data within IoT ecosystems. A collaborative cloud-edge framework emerges as a dependable option for deploying IoT blockchains; however, energy-efficient hardware support on the edge remains insufficient. To resolve this issue, this study introduces a low-power System on Chip (SoC) integrated with a specialized secure coprocessor to handle data on-chain processes. To mitigate physical-level security risks, the SoC incorporates a trusted computing architecture based on dual RISC-V cores. Experimental results using an FPGA platform reveal that the proposed SoC achieves a 12.1-fold performance enhancement for complete data on-chain processing tasks compared to the high-performance Intel i9-13950HX CPU, with total power consumption limited to just 0.579 W.

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基于RISC-V的SoC，用于物联网边缘设备中的区块链数据集成

物联网（IoT）的广泛发展大大增加了对强大数据交互机制的需求，使数据安全成为一个关键挑战。区块链技术以其分散式架构为特点，为物联网生态系统中的数据管理提供了一种创新的解决方案。协作式云边缘框架成为部署物联网区块链的可靠选择；然而，边缘的高能效硬件支持仍然不足。为了解决这个问题，本研究引入了一个低功耗的片上系统（SoC），集成了一个专门的安全协处理器来处理数据链上的过程。为了降低物理层面的安全风险，SoC采用了基于双RISC-V内核的可信计算架构。使用FPGA平台的实验结果表明，与高性能Intel i9-13950HX CPU相比，所提出的SoC在完成数据链处理任务时实现了12.1倍的性能提升，总功耗仅为0.579 W。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.