Microelectronics Journal最新文献_第2页

On-chip Wi-Fi filter with FBW of 16.3 % and IL of 1.8 dB using novel T-type transmission zeros structure 采用新型 T 型传输零点结构的片上 Wi-Fi 滤波器，FBW 为 16.3%，IL 为 1.8 dB

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-10-22 DOI: 10.1016/j.mejo.2024.106448

Bukun Xu, Yuhan Cao, Bo Yuan, Gaofeng Wang

引用次数: 0

A lightweight dual-link accelerated authentication protocol based on NLFSR-XOR APUF 基于 NLFSR-XOR APUF 的轻量级双链路加速认证协议

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-10-22 DOI: 10.1016/j.mejo.2024.106446

Yuanfeng Xie, Hanqing Luo, Liping Liang, Junhong Gan

{"title":"A lightweight dual-link accelerated authentication protocol based on NLFSR-XOR APUF","authors":"Yuanfeng Xie, Hanqing Luo, Liping Liang, Junhong Gan","doi":"10.1016/j.mejo.2024.106446","DOIUrl":"10.1016/j.mejo.2024.106446","url":null,"abstract":"<div><div>Physical Unclonable Function (PUF) circuits, as a lightweight hardware security primitive, can provide reliable authentication for resource-constrained Internet of Things (IoT) devices. However, in real-time environments and systems, authentication of embedded devices has strict requirements on resources and low latency. Therefore, this paper proposes a lightweight dual-link accelerated authentication protocol design based on NLFSR-XOR APUF, through the study of Non-Linear Feedback Shift Registers (NLFSR) and XOR APUF circuits. First, the scheme utilizes the symmetric path delay deviation characteristics of APUF and the complexity of NLFSR state transitions to form a nonlinear output function that changes with the challenge signal. Then, a lightweight and attack-resistant authentication protocol is established by combining the random probability of shuffling array bits with the XOR confusion mechanism. Finally, the advantages of GPU parallel computing and AES T-table reconfiguration scheme are used to achieve an accelerated and side-channel attack-resistant authentication protocol. Experimental results show that the PUF circuit can effectively resist various modeling attacks, including logistic regression (LR), artificial neural network (ANN), and support vector machine (SVM). The security of the protocol has been formally verified, and the prototype has been implemented on the Xilinx xc100T development board, effectively resisting deception attacks, physical attacks, and modeling attacks. The protocol's area overhead in terms of LUT and encryption time is reduced by 58.6 % and 67.8 %, respectively, compared to similar protocols.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-10-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142528249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A low power low phase noise wide frequency range PLL 低功耗、低相位噪声、宽频率范围 PLL

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-10-21 DOI: 10.1016/j.mejo.2024.106441

Tiehu Li, Chaodong Guo, Wei Zhang, Jintao Huang, Jun Zeng, Jun-an Zhang

引用次数: 0

A fin-gate p-GaN HEMT with high threshold voltage and improved dynamic performance 具有高阈值电压和更佳动态性能的鳍式栅 p-GaN HEMT

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-10-19 DOI: 10.1016/j.mejo.2024.106442

Lingyan Shen , Xuetong Zhou , Li Zheng , Xinhong Cheng

{"title":"A fin-gate p-GaN HEMT with high threshold voltage and improved dynamic performance","authors":"Lingyan Shen , Xuetong Zhou , Li Zheng , Xinhong Cheng","doi":"10.1016/j.mejo.2024.106442","DOIUrl":"10.1016/j.mejo.2024.106442","url":null,"abstract":"<div><div>A novel fin-gate p-GaN (FPG) HEMT is proposed to simultaneously increase threshold voltage (V<sub>th</sub>) and improve dynamic performance of the p-GaN HEMT. The fin-gate structure works as a normally-on p-channel MESFET between gate and source by forming a Schottky-type contact on sidewall and a source-connected Ohmic-type contact on top of the fin. Thus, the V<sub>th</sub> can change with the shutdown voltage of the p-channel MESFET, which can be modulated by the doping concentration and width of the fin-p-GaN. By optimizing the fin structure, a high positive V<sub>th</sub> of 4V is achieved without transconductance and breakdown voltage degradation in this work. It breaks the restriction between V<sub>th</sub> and on-resistance for conventional p-GaN HEMT. The dynamic characteristics of the FPG HEMT are investigated by SPICE simulations. Owing to the well-grounded p-GaN through the normally-on MESFET, the recovery process of the dynamic shift in V<sub>th</sub> (ΔV<sub>th</sub>) after on/off-state stress can be accelerated by two orders of magnitude. It means an imperceptible dynamic degradation and a great potential in high frequency application for the FPG HEMT.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142528248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A passive self-excited oscillation AC low-voltage energy harvesting circuit without a bridge 无电桥无源自激振荡交流低压能量采集电路

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-10-18 DOI: 10.1016/j.mejo.2024.106439

Jiaheng Pan , Yanwei Sun , Yizhou Qi , Xing Liang , Yinshui Xia , Xiudeng Wang , Huakang Xia , Shengyao Jia , Ge Shi

引用次数: 0

Exploring thermal effects of advanced backside power delivery network beyond 3 nm node 探索 3 纳米节点之后先进背面功率传输网络的热效应

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-10-15 DOI: 10.1016/j.mejo.2024.106440

Haoyu Zhang , Linlin Cai , Haifeng Chen , Binyu Yin , Wangyong Chen

{"title":"Exploring thermal effects of advanced backside power delivery network beyond 3 nm node","authors":"Haoyu Zhang , Linlin Cai , Haifeng Chen , Binyu Yin , Wangyong Chen","doi":"10.1016/j.mejo.2024.106440","DOIUrl":"10.1016/j.mejo.2024.106440","url":null,"abstract":"<div><div>Backside Power Delivery Networks (BSPDNs) address scaling issues by relocating power, boosting efficiency and density. However, thermal effects pose challenges. In this work, a comprehensive thermal analysis of BSPDN is performed to elaborate the key modulation factors and possible optimization approaches, where the specific backside metal layers are constructed to investigate the impacts of operating conditions, via distribution and materials on thermal effects. To improve the simulation efficiency, the effective thermal conductivity is employed to simplify the Nanosheet (NSH) FET based front-end-of-line (FEOL) and other layers at the 3 nm technology node. Results show that non-uniform via distribution in BSPDN causes temperature fluctuations, but augmenting Backside Via counts effectively mitigates local peak temperature increases from higher power. For BSPDN, backside cooling solutions outperform frontside in efficiency, particularly at high via densities. Using high thermal conductivity inter-metal dielectric (IMD) materials significantly reduces global temperature rise and fluctuations from non-uniform vias in BSPDN, enhancing PDN design flexibility.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-10-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142445690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

High efficiency AOT-controlled boost converter with pseudo-constant switching frequency 具有伪恒定开关频率的高效 AOT 控制升压转换器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-10-12 DOI: 10.1016/j.mejo.2024.106438

Xinkai Miao, Yinshui Xia, Xiudeng Wang, Haizhun Wang, Yu Tong

{"title":"High efficiency AOT-controlled boost converter with pseudo-constant switching frequency","authors":"Xinkai Miao, Yinshui Xia, Xiudeng Wang, Haizhun Wang, Yu Tong","doi":"10.1016/j.mejo.2024.106438","DOIUrl":"10.1016/j.mejo.2024.106438","url":null,"abstract":"<div><div>An on-time generator for boost converters is proposed to achieve an adaptive on-time (AOT) control with pseudo-constant frequency in continuous conduction mode (CCM). Since the first-order parasitic effect of the components and devices is considered in the design of the on-time generator, the switching frequency (<span><math><mrow><msub><mi>f</mi><mrow><mi>s</mi><mi>w</mi></mrow></msub></mrow></math></span>) variation of the boost converter in CCM can be better suppressed with the load current (<span><math><mrow><msub><mi>I</mi><mrow><mi>L</mi><mi>O</mi><mi>A</mi><mi>D</mi></mrow></msub></mrow></math></span>), input voltage (<span><math><mrow><msub><mi>V</mi><mrow><mi>I</mi><mi>N</mi></mrow></msub></mrow></math></span>) and output voltage (<span><math><mrow><msub><mi>V</mi><mrow><mi>O</mi><mi>U</mi><mi>T</mi></mrow></msub></mrow></math></span>) changes, which can effectively solve the EMI noise problem. In addition, the idea of capacitor pre-charging is applied to simplifying circuit complexity. Meanwhile, an on-demand modulation strategy is applied to improve the conversion efficiency. Simulation results show that the boost converter based on the proposed on-time generator can realize the <span><math><mrow><msub><mi>f</mi><mrow><mi>s</mi><mi>w</mi></mrow></msub></mrow></math></span> variation of <span><math><mrow><mn>0.4</mn></mrow></math></span> % in case of 200 mA <span><math><mrow><msub><mi>I</mi><mrow><mi>L</mi><mi>O</mi><mi>A</mi><mi>D</mi></mrow></msub></mrow></math></span> change. Moreover, the <span><math><mrow><msub><mi>V</mi><mrow><mi>I</mi><mi>N</mi></mrow></msub></mrow></math></span> may range from 0.8 to 1.5 V, the <span><math><mrow><msub><mi>V</mi><mrow><mi>O</mi><mi>U</mi><mi>T</mi></mrow></msub></mrow></math></span> is set to 1.8 V, and the peak efficiency of the simulation is 96.9 %.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-10-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142445692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

RSD-based high-performance radix-4 Montgomery Modular Multiplication for Elliptic Curve Cryptography 基于 RSD 的高性能弧度-4 蒙哥马利模块乘法椭圆曲线密码学

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-10-10 DOI: 10.1016/j.mejo.2024.106433

Shilei Zhao, Jiwen Zheng, Yutong Shao, Hai Huang, Zhiwei Liu, Bin Yu, Ziyue Zhang

{"title":"RSD-based high-performance radix-4 Montgomery Modular Multiplication for Elliptic Curve Cryptography","authors":"Shilei Zhao, Jiwen Zheng, Yutong Shao, Hai Huang, Zhiwei Liu, Bin Yu, Ziyue Zhang","doi":"10.1016/j.mejo.2024.106433","DOIUrl":"10.1016/j.mejo.2024.106433","url":null,"abstract":"<div><div>This paper proposes a high-performance radix-4 Montgomery Modular Multiplication (MMM) algorithm and its corresponding hardware architecture for Elliptic Curve Cryptography (ECC), in which the quotient and the partial product accumulation are computed in parallel in each iteration. Additionally, in this MMM, the Redundant Signed Digit (RSD) representation and the Signed Digit Adder (SDA) are used to eliminate the long carry chain and achieve parallel computation, as well as remove pre-computation and integrate modular reduction operations. Our MMM algorithm is implemented in 256-bit and 1024-bit versions on Xilinx Virtex-6 and Virtex-7 FPGAs, respectively. It consumes only 1.55k/10.18k Look-Up Tables (LUTs), takes 133/517 clock cycles, and runs at maximum frequencies of 558.8/641.7 MHz. According to the comparison in terms of Area Time Product (ATP), our design can achieve the ATP of 0.369 over the 256-bit NIST prime domain, which is approximately half of that of the state-of-the-art works. The Scalar Point Multiplication (SPM) scheme using this MMM algorithm consumes 14.19k LUTs and completes a single Scalar Point Multiplication (SPM) operation in 0.217 ms, and it also has a lower ATP than most other SPM algorithms currently in existence.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142445691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A high sensitivity biosensor based on fin-type electron-hole bilayer TFET 基于鳍式电子-空穴双层 TFET 的高灵敏度生物传感器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-10-10 DOI: 10.1016/j.mejo.2024.106437

Hu Liu, Peifeng Li, Lei Pan, Xiaoyu Zhou, Pengyu Wang, Yubin Li

{"title":"A high sensitivity biosensor based on fin-type electron-hole bilayer TFET","authors":"Hu Liu, Peifeng Li, Lei Pan, Xiaoyu Zhou, Pengyu Wang, Yubin Li","doi":"10.1016/j.mejo.2024.106437","DOIUrl":"10.1016/j.mejo.2024.106437","url":null,"abstract":"<div><div>A novel biosensor is proposed based on the fin-type electron-hole bilayer tunnel field-effect transistor, and its sensitivity is investigated in detail using numerical simulation. Single vertical nanocavity in this biosensor facilitates the injection and filling of biomolecules and simplifies the fabrication process. This biosensor’s operation depends on the line-tunneling occurring between electron-hole bilayer, making it more sensitive to biomolecules. By investigating effects of neutral and charged biomolecules, biomolecules’ irregular distribution, probe position, and device structure on this biosensor, it follows that it is more sensitive to positively charged biomolecules with higher dielectric constant and charge density. Furthermore, it has higher sensitivity when biomolecules show an increasing distribution and the probe is located in the lower half of the nanocavity and has high filling rate. Calculation shows that at a low operating voltage of 0.5 V, its threshold voltage sensitivity, on-state current sensitivity, and subthreshold swing sensitivity are as high as 740 mV, 6.0 × 10<sup>3</sup>, and 0.92, respectively.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142415884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Cryo-CMOS 10-bit 60-MS/s SAR ADC with common-mode variation suppression switching scheme and gain boosting dynamic comparator 具有共模变化抑制开关方案和增益提升动态比较器的 Cryo-CMOS 10 位 60-MS/s SAR ADC

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-10-09 DOI: 10.1016/j.mejo.2024.106435

Chia-Wei Pai , Ken Uchida , Munehiro Tada , Hiroki Ishikuro

{"title":"A Cryo-CMOS 10-bit 60-MS/s SAR ADC with common-mode variation suppression switching scheme and gain boosting dynamic comparator","authors":"Chia-Wei Pai , Ken Uchida , Munehiro Tada , Hiroki Ishikuro","doi":"10.1016/j.mejo.2024.106435","DOIUrl":"10.1016/j.mejo.2024.106435","url":null,"abstract":"<div><div>This paper presents a 10-bit 60-MS/s SAR ADC using an energy-efficient common-mode variation suppression (CMVS) switching scheme. The proposed CMVS switching scheme reduces energy consumption by about 92 % compared to the conventional scheme. Also, it narrows the common-mode variation to 16.6 % <span><math><mrow><msub><mi>V</mi><mrow><mi>D</mi><mi>D</mi></mrow></msub></mrow></math></span>. It improves the accuracy of the SAR ADC and makes the comparator and SAR ADC operate at the best-performance region. The proposed comparator adopts a gain boosting dynamic capacitive pre-amplifier to enhance the amplification and accelerate the comparison speed. The regeneration latch keeps the cross-coupled inverter structure to ensure high-speed regeneration. The input pair of the latch suppresses the through current while decreasing the regeneration speed. Therefore, an auxiliary input pair is added to enhance the regeneration speed. The SAR ADC is designed and simulated using 65-nm Cryo-CMOS technology with <span><math><mrow><msub><mi>V</mi><mrow><mi>D</mi><mi>D</mi></mrow></msub></mrow></math></span> = 1.2 V. At <span><math><mrow><mi>T</mi></mrow></math></span> = 300 K, it achieves a FoM of 15.39 fJ/conversion-step with 55-MS/s. At <span><math><mrow><mi>T</mi></mrow></math></span> = 4 K, it achieves a FoM of 14.15 fJ/conversion-step with 60-MS/s.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142445693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0