Microelectronics Journal最新文献_第2页

A true random number generator based on autonomous Boolean network with imbalanced node oscillation rings 基于不平衡节点振荡环自治布尔网络的真随机数生成器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-19 DOI: 10.1016/j.mejo.2025.106694

Maoxiang Yi , Zhengwen Liu , Zihao Miao , Yingchun Lu , Huaguo Liang , Lixiang Ma

{"title":"A true random number generator based on autonomous Boolean network with imbalanced node oscillation rings","authors":"Maoxiang Yi , Zhengwen Liu , Zihao Miao , Yingchun Lu , Huaguo Liang , Lixiang Ma","doi":"10.1016/j.mejo.2025.106694","DOIUrl":"10.1016/j.mejo.2025.106694","url":null,"abstract":"<div><div>True random number generators have broad application prospects in the fields of hardware and information security. In order to improve the throughput of true random number generator with lower hardware overhead, an autonomous Boolean network with coupled basic logic units and imbalanced node oscillating rings is constructed as the entropy source. A first-order high-frequency oscillation loop is used to enhance the network refresh frequency, and a high entropy chaotic signal is generated through multi-level nonlinear coupling and amplification of the node output signals. Each output signal of the entropy circuit is sampled with D Flip-Flop and the result is sent to a post-processing circuit composed of XOR network, where the true random number is obtained. The proposed TRNG is implemented on Xilinx A7 FPGA development board. The sampled output data is grabbed and extracted in real time using the ChipScope IP module, and then transferred to computer for experimental testing. NIST SP800-22 and SP800-90B randomness tests are performed on the generated data, and some other important performances such as deviation, autocorrelation, and maximum Lyapunov exponent are also evaluated. The results show that at a throughput of 750Mbps, the proposed TRNG can generate true random numbers with entropy values of 0.996323bps, low deviation and low autocorrelation, being also of low hardware overhead.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"160 ","pages":"Article 106694"},"PeriodicalIF":1.9,"publicationDate":"2025-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143864434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 20-bit 1MS/s SAR ADC suppressing the dynamic error caused by thermal effect in the static comparator 一个20位1MS/s的SAR ADC抑制了静态比较器中由于热效应引起的动态误差

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-19 DOI: 10.1016/j.mejo.2025.106695

Zhenyu Zhu, Yuzhou Xiong, Yanbo Zhang, Zhangming Zhu

{"title":"A 20-bit 1MS/s SAR ADC suppressing the dynamic error caused by thermal effect in the static comparator","authors":"Zhenyu Zhu, Yuzhou Xiong, Yanbo Zhang, Zhangming Zhu","doi":"10.1016/j.mejo.2025.106695","DOIUrl":"10.1016/j.mejo.2025.106695","url":null,"abstract":"<div><div>High-precision analog-to-digital converters (ADCs) play a crucial role in modern mixed-signal systems, particularly in applications demanding low noise and high resolution. This paper presents a high-precision successive approximation register (SAR) ADC implemented in a 180 nm process. A coarse SAR ADC quantizes the 8-bit most significant bits (MSBs), and a fine SAR ADC processes the remaining 12-bit least significant bits (LSBs). Both SAR ADCs simultaneously sample the input signal, and the fine ADC concurrently copies the 8-bit MSB digital code after the coarse ADC completes quantization. This approach effectively prevents large differential voltages at the comparator's input, thereby eliminating dynamic errors caused by excessive current differences in the load resistance. To further enhance performance, a four-stage pre-amplifier with output offset cancellation is employed as the comparator's pre-amplifier. Careful tuning of the pre-amplifier stages minimizes the comparator's overall bandwidth without compromising accuracy. Simulation results demonstrate an offset voltage of 13.98 μV, input-referred noise of 12.18 μV. When transient noise is enabled, FFT analysis shows a Signal-to-Noise and Distortion Ratio (SNDR) of 106.260 dB. With a power consumption of 40 mW, the Schreier figure of merit (FoM) reaches 177.2 dB, confirming the proposed ADC's suitability for high-precision applications.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"160 ","pages":"Article 106695"},"PeriodicalIF":1.9,"publicationDate":"2025-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143864435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Exponential-incremental quantization-based calibration for capacitor mismatch in high-precision SAR ADCs 高精度SAR adc中电容失配的指数增量量化校准

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-18 DOI: 10.1016/j.mejo.2025.106696

Zheyu Zhang, Yuzhou Xiong, Yanbo Zhang, Shubin Liu, Zhangming Zhu

引用次数: 0

Drain side pocket-based Germanium nanotube tunnel FET for low power complementary ternary inverter 用于低功率互补三元逆变器的漏侧口袋型锗纳米管隧道场效应管

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-17 DOI: 10.1016/j.mejo.2025.106692

Navneet Kaur Saini , Nitish Kumar , Raghvendra Sahai Saxena , Anuj Dhawan , M. Jagadesh Kumar

{"title":"Drain side pocket-based Germanium nanotube tunnel FET for low power complementary ternary inverter","authors":"Navneet Kaur Saini , Nitish Kumar , Raghvendra Sahai Saxena , Anuj Dhawan , M. Jagadesh Kumar","doi":"10.1016/j.mejo.2025.106692","DOIUrl":"10.1016/j.mejo.2025.106692","url":null,"abstract":"<div><div>In this article, a drain side pocket-based Germanium nanotube tunnel field-effect transistor (DP-LNTFET) is proposed for a low-power standard ternary inverter (STI), which operates at 0.5 V. This device exhibits gate-bias-independent channel-to-pocket tunneling at low gate bias, and at higher gate bias, it transitions to within source line tunneling. These unique characteristics result in a third output voltage state in the conventional binary voltage transfer characteristics (VTCs). Thus, a simple implementation of the STI is designed by replacing with the N/P type DP-LNTFET in a conventional binary inverter. It shows a significant ∼156 % improvement in static noise margin (SNM) and ∼97 % improvement in the power-delay-product (PDP), compared to the STI implemented with the tunneling ternary CMOS device (T-CMOS). These advantages show promising solution for low-power applications using DP-LNTFET devices. Further, the impact of process variations on the performance of the STI is also analyzed, where the DP-LNTFET shows invariance to doping profile variations at the pocket and drain junction, thereby reducing doping complexity.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"160 ","pages":"Article 106692"},"PeriodicalIF":1.9,"publicationDate":"2025-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143848021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A cross-matrix arbiter PUF with high reliability and ML-resistance for IoT device security 一种具有高可靠性和抗ml的跨矩阵仲裁PUF，用于物联网设备安全

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-14 DOI: 10.1016/j.mejo.2025.106674

Zhangqing He , Junming Zhang , Xinrui Zhu , Siyu Luo , Zhengya Zhang , Zhou Huang

{"title":"A cross-matrix arbiter PUF with high reliability and ML-resistance for IoT device security","authors":"Zhangqing He , Junming Zhang , Xinrui Zhu , Siyu Luo , Zhengya Zhang , Zhou Huang","doi":"10.1016/j.mejo.2025.106674","DOIUrl":"10.1016/j.mejo.2025.106674","url":null,"abstract":"<div><div>Physical unclonable function is considered a promising hardware security primitive for resource-constrained IoT devices. Arbiter PUF is one of the most well-known strong PUFs, which suffers from vulnerability to machine learning attacks and low reliability. In this paper, a high reliability and machine learning resistant cross-matrix (CM) arbiter PUF is proposed, which realizes the diversity of signal transmission paths through interstage cross structures, and adds inter row cross-feed loops between different arbiter PUFs to nonlinearized the circuit, which considerably enhances the resistance to machine learning attacks. A reliability enhancement model is also proposed to select the pair with the largest delay difference as the output from multiple delay paths, which significantly improves the reliability of CMAPUF. A mathematical model is developed to analyze the proposed CMAPUF and then we implement the circuit on Xilinx Artix-7 FPGA. The test results show that CMAPUF can effectively resist several widely used machine learning attacks with prediction accuracy below 60 % under 10<sup>6</sup> training samples, while its bit error rate (BER) at normal condition (1V, 25 °C) is 0.55 % and worst BER when the environmental change is 1.56 %.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"160 ","pages":"Article 106674"},"PeriodicalIF":1.9,"publicationDate":"2025-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143843255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 16-channel, multi-level Time-to-Digital Converter for high precision ToF measurement 用于高精度ToF测量的16通道，多级时间-数字转换器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-12 DOI: 10.1016/j.mejo.2025.106669

Ziwei Zhao , Ran Zheng , Jia Wang , Xiaomin Wei , Feifei Xue , Ruiguang Zhao , Yongcai Hu

引用次数: 0

A 10–15 GHz four-antenna phased array beamforming receiver with eight-simultaneous beams in 55-nm CMOS Technology 基于55纳米CMOS技术的10-15 GHz四天线相控阵波束形成接收机

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-11 DOI: 10.1016/j.mejo.2025.106670

Bin Li , Shubo Dun , Qinghui Song , Haifu Zhang , Xiaodong Cui , Hanyang Luo , Geliang Yang

{"title":"A 10–15 GHz four-antenna phased array beamforming receiver with eight-simultaneous beams in 55-nm CMOS Technology","authors":"Bin Li , Shubo Dun , Qinghui Song , Haifu Zhang , Xiaodong Cui , Hanyang Luo , Geliang Yang","doi":"10.1016/j.mejo.2025.106670","DOIUrl":"10.1016/j.mejo.2025.106670","url":null,"abstract":"<div><div>This paper demonstrates a 10–15 GHz four-antenna phased array beamforming receiver with eight-simultaneous beams. The full-connected multibeam architecture is adopted to maximize the beamforming gain. To mitigate the design complexity and large chip area-consumption caused by the multibeam combination, a compact active multibeam combining technique is proposed, which features current-domain phase shifted signal combining and compact passive signal connection network. Implemented in a 55-nm CMOS process, the receiver consumes a current of 1100 mA with a 1.2 V supply. From 10 to 15 GHz, the receiver achieves a 360° phase shifting range with a 6-bit resolution, and the root mean square (RMS) phase is less than 3°. The 6-bit attenuator in each output channel achieves less than 0.4 dB root mean square (RMS) gain error. The receiver demonstrates a gain of 20 dB (20.5 dB), a 5.5 dB (7.6 dB) noise figure, and an input-referred 1 -dB gain compression point (IP<sub>1dB</sub>) of −20 dBm (−22 dBm) at 10 GHz (15 GHz), respectively. The chip size, including pads, is only 3.6 × 5.4 mm<sup>2</sup>.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"160 ","pages":"Article 106670"},"PeriodicalIF":1.9,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143825961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Algorithm of the inter-channel mismatches calibration in TIADC TIADC信道间失配校正算法

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-11 DOI: 10.1016/j.mejo.2025.106688

Chengjie Wang, Shengmin Yang, Yuhua Liang

{"title":"Algorithm of the inter-channel mismatches calibration in TIADC","authors":"Chengjie Wang, Shengmin Yang, Yuhua Liang","doi":"10.1016/j.mejo.2025.106688","DOIUrl":"10.1016/j.mejo.2025.106688","url":null,"abstract":"<div><div>To address the issues in existing algorithms related to calibration accuracy, hardware utilization, or the trade-off between calibration speed and accuracy, this paper proposes a fully digital background calibration method including parallel and serial architecture, which can reduce hardware utilization and supports the expansion to an arbitrary number of channels.</div><div>We performed board-level verification on an FPGA for the proposed algorithm. The results of the FPGA board-level verification match those of the MATLAB behavioral simulation. At an input frequency of 0.025 <span><math><mrow><msub><mi>f</mi><mi>s</mi></msub></mrow></math></span>, the SNDR and SFDR improved by 8.59 dB and 11.54 dB, respectively, and the effective number of bits (ENOB) increased by 1.42 bits. At an input frequency of 0.05 <span><math><mrow><msub><mi>f</mi><mi>s</mi></msub></mrow></math></span>, the SNDR and SFDR improved by 20.89 dB and 13.65 dB, respectively, and the ENOB increased by 2.27 bits. At an input frequency of 0.2 <span><math><mrow><msub><mi>f</mi><mi>s</mi></msub></mrow></math></span>, the SNDR and SFDR improved by 11.86 dB and 17.89 dB, respectively, and the ENOB increased by 1.97 bits. The output layout size was 500 μm × 550 μm.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"160 ","pages":"Article 106688"},"PeriodicalIF":1.9,"publicationDate":"2025-04-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143825962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 15.4 nW, 59 ppm/∘C CMOS voltage reference circuit with process and temperature compensation 15.4 nW， 59 ppm/ C的CMOS电压基准电路，带有工艺和温度补偿

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-10 DOI: 10.1016/j.mejo.2025.106664

Annan Wang , Yuchen Sun , Zhang Zhang

{"title":"A 15.4 nW, 59 ppm/∘C CMOS voltage reference circuit with process and temperature compensation","authors":"Annan Wang , Yuchen Sun , Zhang Zhang","doi":"10.1016/j.mejo.2025.106664","DOIUrl":"10.1016/j.mejo.2025.106664","url":null,"abstract":"<div><div>This article presents a low-power CMOS voltage reference circuit with process and temperature compensation. The design employs a current source circuit to generate a bias current that shows process and temperature variations complementary to those of the output voltage of the stacked diode connected MOS transistor (SDMT). By adjusting the transistor size and current mirror ratio, the bias current exhibits the opposite temperature coefficient (TC) and process skew to that of the SDMT, thus achieving process and temperature compensation. This voltage reference is implemented using a standard 65 nm CMOS process, with a core chip area of <span><math><mrow><mn>5500</mn><mspace></mspace><mi>μ</mi><msup><mrow><mi>m</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span>. At room temperature, measurements were taken on 18 chips, with an average output reference voltage of 335.7 mV and a standard deviation of 1.02 mV (<span><math><mi>σ</mi></math></span>/<span><math><mi>μ</mi></math></span> = 0.31%). Over the temperature range of −40 °C to 120 °C, the average temperature coefficient is 59 ppm/<span><math><msup><mrow></mrow><mrow><mo>∘</mo></mrow></msup></math></span>C. Within the supply voltage range of 0.7 V–1.5 V, the line sensitivity is 0.21%/V, the power supply rejection ratio (PSRR) at 100 Hz is −50 dB, and the power consumption at 0.7 V is 15.4 nW.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"160 ","pages":"Article 106664"},"PeriodicalIF":1.9,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143821089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An adaptive background light rejection technique with integrated laser interference filter for direct time-of-flight sensors 用于直接飞行时间传感器的集成激光干扰滤波器自适应背景光抑制技术

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-10 DOI: 10.1016/j.mejo.2025.106675

Huazhen Wang, Kaiming Nie, Jiangtao Xu

{"title":"An adaptive background light rejection technique with integrated laser interference filter for direct time-of-flight sensors","authors":"Huazhen Wang, Kaiming Nie, Jiangtao Xu","doi":"10.1016/j.mejo.2025.106675","DOIUrl":"10.1016/j.mejo.2025.106675","url":null,"abstract":"<div><div>To suppress the varying background light and laser interference in direct time-of-flight (DToF) sensors, this paper presents an adaptive pixel-to-pixel coincidence detection and smart time gating technique. Each pixel contains one single-photon avalanche diode and shares signals with surrounding pixels. The coincidence detection level is automatically adjusted based on the coincidence of the signal and noise. Time gating is generated based on the output of a time-to-digital converter. The technique is implemented through circuit design using a 110 nm process and validated through behavioral modeling and circuit simulations. Simulation results show the technique achieves success rates (SRs) exceeding 60% and signal-to-noise ratios (SNRs) above 3 under background light levels ranging from 10 to 100 klux. It maintains SRs exceeding 50% and SNRs above 2 for target distances ranging from 0.5 to 46.5 m. It ensures signal-to-interference ratios above 1 under laser interference. This technique enables DToF sensors to operate under varying background light levels and effectively filters out laser interference.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"160 ","pages":"Article 106675"},"PeriodicalIF":1.9,"publicationDate":"2025-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143821178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0