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Miniaturized bandpass filter with ultrawide-stopband and high selectivity using glass-based IPD technology 利用玻璃基 IPD 技术实现超宽截止带和高选择性的微型带通滤波器
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-09-12 DOI: 10.1016/j.mejo.2024.106402
{"title":"Miniaturized bandpass filter with ultrawide-stopband and high selectivity using glass-based IPD technology","authors":"","doi":"10.1016/j.mejo.2024.106402","DOIUrl":"10.1016/j.mejo.2024.106402","url":null,"abstract":"<div><p>A miniaturized bandpass filter (BPF) with ultrawide-stopband and high selectivity performance is proposed by virtue of glass-based integrated passive devices (IPD) technology. The proposed BPF consists of two modified second-order units and an impedance inverter. In the modified second-order units, two capacitors are added to the traditional second-order Chebyshev bandpass filter, which can generate two additional transmission zeros locating in the lower and upper bands, respectively. Moreover, these two modified second-order units are cascaded to improve the selectivity and achieve the ultrawide-stopband of the proposed BPF. In addition, the cascaded impedance inverter is introduced to further improve impedance matching of the proposed BPF. The proposed BPF is fabricated using glass-based IPD technology and measured by on-wafer probing. The fabricated BPF has a compact size of 1.0 mm × 1.0 mm × 0.35 mm. The measured results show that the fabricated BPF can cover the wide operating band from 3.3 GHz to 5.0 GHz with an insertion loss of 1.4 dB, a return loss better than 17.5 dB in the passband, and an upper stopband suppression better than 21.6 dB up to 43.5 GHz (10.48<em>f</em><sub>0</sub>). In addition, the fabricated BPF can achieve a good frequency selectivity with a rectangular coefficient of 1.33. The simulated and measured results exhibit good agreements.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142243649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High-precision vernier-type optoelectronic integrated chip design 高精度游标型光电集成芯片设计
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-09-12 DOI: 10.1016/j.mejo.2024.106400
{"title":"High-precision vernier-type optoelectronic integrated chip design","authors":"","doi":"10.1016/j.mejo.2024.106400","DOIUrl":"10.1016/j.mejo.2024.106400","url":null,"abstract":"<div><div>An optoelectronic integrated chip combining vernier coding and Gray coding is designed in this study. The structure that combines two encoding methods provides a more accurate delineation of the angles. This improves the accuracy of angle measurement. In addition, the chip incorporates a specially shaped photodiode array. It is designed with a special boundary function to filter out odd harmonics. The chip also integrates a fully differential amplifier to reduce common mode noise and filter out even harmonics. Based on the 0.35 μm CMOS process, the chip area is 3.41 mm × 2.91 mm. The measurement shows that the chip can operate normally in the ambient temperature of −40 °C–125 °C. Moreover, the chip can output sinusoidal signals and Gray code signals with good orthogonality and accuracy when the motor speed is within 3000 rpm.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142311583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of a miniaturized multi resonance resonator based highly selective dual wideband bandpass filter 设计基于微型多谐振共振器的高选择性双宽带带通滤波器
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-09-11 DOI: 10.1016/j.mejo.2024.106411
{"title":"Design of a miniaturized multi resonance resonator based highly selective dual wideband bandpass filter","authors":"","doi":"10.1016/j.mejo.2024.106411","DOIUrl":"10.1016/j.mejo.2024.106411","url":null,"abstract":"<div><p>This paper presents the design of a highly selective dual-wideband bandpass filter. The filter is designed by using multi-resonance resonator consisting of two stub-loaded step impedance resonators separated by an inter-digital capacitor. The inter-digital capacitor generates capacitive coupling, resulting in multiple resonating modes. The proposed filter generates two passband frequencies centered at 5.75 GHz and 11.5 GHz. Experimental measurements show that the maximum insertion loss in the passbands is 0.83 dB and 0.87 dB, while the reflection losses are better than 10.8 dB and 12.6 dB, respectively. The resonant frequencies can be adjusted by changing the length of the loaded stubs. The proposed dual-wideband bandpass filter offers improved out-of-band rejection and selectivity by generating seven transmission poles and seven transmission zeros around both passbands. The experimental results confirm the effectiveness of the proposed filter. Furthermore, the filter has a compact size of <span><math><mrow><mrow><mo>(</mo><mn>0</mn><mo>.</mo><mn>61</mn><mo>×</mo><mn>0</mn><mo>.</mo><mn>66</mn><mo>)</mo></mrow><msub><mrow><mi>λ</mi></mrow><mrow><mi>g</mi></mrow></msub></mrow></math></span>, making it suitable for integration into microwave sensing devices.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S1879239124001152/pdfft?md5=4818d63dafffd47325c9ae13d3aa4482&pid=1-s2.0-S1879239124001152-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142172726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Step thickness drift region automatic design of SOI LDMOS using physics-inspired constrained simulated annealing algorithm 利用物理学启发的约束模拟退火算法自动设计 SOI LDMOS 的阶跃厚度漂移区
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-09-07 DOI: 10.1016/j.mejo.2024.106410
{"title":"Step thickness drift region automatic design of SOI LDMOS using physics-inspired constrained simulated annealing algorithm","authors":"","doi":"10.1016/j.mejo.2024.106410","DOIUrl":"10.1016/j.mejo.2024.106410","url":null,"abstract":"<div><p>The introduction of the step thickness drift region (ST) technique has increased the design complexity of silicon-on-insulator (SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS). This paper proposes a physics-inspired automatic optimization method for the ST structure of SOI LDMOS using constrained simulated annealing algorithm. Since breakdown voltage (BV) and specific on-resistance (R<sub>on,sp</sub>) need to be optimized simultaneously, an optimization function based on Baliga's Figure of Merit (BFOM) is introduced. Besides, constraints are introduced to ensure that BV is greater than the initial BV and R<sub>on,sp</sub> is less than the initial R<sub>on,sp</sub>. Results demonstrate that the BFOM values increase by an average of 134.9 %, 163.6 %, and 113.8 % when the breakdown occurs at the N<sup>+</sup>N junction, PN junction, and in-the-body after optimizing the ST structure, respectively. Besides, introducing constraints during the automatic design process allows for the simultaneous optimization of both the BV and R<sub>on,sp</sub>. Furthermore, the proposed method is also efficient, with 86 % of the optimization design processes completed within 18 seconds.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142148724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An LC-tank based DCO for low-power high-speed applications using full-custom nMOS-type varactors 使用全定制 nMOS 型变容器的基于 LC 罐的 DCO，适用于低功耗高速应用
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-09-06 DOI: 10.1016/j.mejo.2024.106398
{"title":"An LC-tank based DCO for low-power high-speed applications using full-custom nMOS-type varactors","authors":"","doi":"10.1016/j.mejo.2024.106398","DOIUrl":"10.1016/j.mejo.2024.106398","url":null,"abstract":"<div><p><span><math><mrow><mi>L</mi><mi>C</mi></mrow></math></span>-tank based Digital Controlled Oscillators (<span><math><mrow><mi>L</mi><mi>C</mi></mrow></math></span>-DCOs) are widely used in digital assisted high-speed data communication systems due to their high quality factor (<span><math><mi>Q</mi></math></span>). Typically, <span><math><mrow><mi>L</mi><mi>C</mi></mrow></math></span>-DCOs incorporate digital-controlled varactors for frequency control. The varactor structure significantly influences oscillator <span><math><mi>Q</mi></math></span> and phase noise performance. In this paper we propose using full-custom varactors built with digitally connected nMOS-type transistors to enhance the varactor <span><math><mi>Q</mi></math></span> by reducing its length. However, parasitic resistance from varactor array interconnection with the <span><math><mrow><mi>L</mi><mi>C</mi></mrow></math></span>-tank can impact the overall oscillator performance. This paper presents a methodology to systematically include the proposed varactor array and its parasitic effects into <span><math><mrow><mi>L</mi><mi>C</mi></mrow></math></span>-DCO design flow. Following the proposed method, an optimal combination of the inductor and varactor array can be accurately determined. As a proof of concept, we designed and manufactured a 23.5-GHz <span><math><mrow><mi>L</mi><mi>C</mi></mrow></math></span>-DCO using 28-nm CMOS RF process. The oscillator exhibits a maximum phase noise of −90.1 dBc/Hz at 1-MHz offset with a power consumption of only 1.71 mW at 1-V supply.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142229125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A temperature compensation technique for constant current LED driver 恒流 LED 驱动器的温度补偿技术
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-09-06 DOI: 10.1016/j.mejo.2024.106396
{"title":"A temperature compensation technique for constant current LED driver","authors":"","doi":"10.1016/j.mejo.2024.106396","DOIUrl":"10.1016/j.mejo.2024.106396","url":null,"abstract":"<div><div>This paper presents the design and implementation of an LED driving chip using TSMC's 0.35 μm Mixed-Signal 2P4M Polycide 3.3V/5V process. The main focus is on designing temperature compensation circuits to reduce variations in LED lighting. Based on the on-chip temperature sensing circuit, the LED driving current can be automatically compensated under various temperatures. We employ a voltage-controlled oscillator(VCO) as a thermometer. The VCO's frequency decreases when the temperature increases. Digital encoders are employed to encode this temperature information. This digital data is then used to automatically control switches, adjusting the current flow to compensate for LED current variations due to temperature changes. All functions were integrated to a silicon chip with about 2.2 mm<sup>2</sup> area. With temperature chamber testing, the range from −20 °C to 120 °C, the results show that the error rate of the driving current can be reduced from 14 % to 0.7 % after temperature compensation.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142311582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 62.5 kHz-BW 92 dB-SNDR noise-shaping SAR ADC with NS-CAL method 采用 NS-CAL 方法的 62.5 kHz-BW 92 dB-SNDR 噪声整形 SAR ADC
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-09-05 DOI: 10.1016/j.mejo.2024.106401
{"title":"A 62.5 kHz-BW 92 dB-SNDR noise-shaping SAR ADC with NS-CAL method","authors":"","doi":"10.1016/j.mejo.2024.106401","DOIUrl":"10.1016/j.mejo.2024.106401","url":null,"abstract":"<div><p>DAC mismatch is a significant error in NS-SAR ADCs, as it introduces essentially nonlinear behavior and limits the number of bits in the DAC array. In this paper, we propose a novel foreground digital calibration method for NS-SAR ADCs. This method, combined with noise shaping technique, improves calibration accuracy and eliminates the impact of error accumulation on high-bit weights. Thus, it increases the number of bits in the DAC array in NS-SAR ADCs, and decreases the noise floor caused by quantization error. We implemented this design using a 110-nm CMOS process. As a result, post-layout simulation shows 92 dB SNDR and 108 dB SFDR under × 16 OSR and 1.5 V supply. Compared with conventional foreground calibration method, the SNDR increases from 81 dB to 92 dB and the SFDR increases from 84 dB to 108 dB with a power consumption of 40 μW, resulting in a FoMs of 182 dB and a FoMw of 15.3 fJ/conversion-step, respectively.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142229124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 28-nm 9T SRAM-based CIM macro with capacitance weighting module and redundant array-assisted ADC 基于 28 纳米 9T SRAM 的 CIM 宏，带电容加权模块和冗余阵列辅助 ADC
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-09-03 DOI: 10.1016/j.mejo.2024.106397
{"title":"A 28-nm 9T SRAM-based CIM macro with capacitance weighting module and redundant array-assisted ADC","authors":"","doi":"10.1016/j.mejo.2024.106397","DOIUrl":"10.1016/j.mejo.2024.106397","url":null,"abstract":"<div><p>In the emerging field of Computing-in-Memory (CIM), this study introduces a 28-nm CMOS-based Static Random Access Memory (SRAM) CIM macro capable of various computational modes, potentially offering a solution to the Von Neumann bottleneck. Beyond traditional SRAM read and write operations, to enhance the flexibility of the CIM macro, a 9T cell is proposed for performing AND, OR, and XNOR operations; a new capacitive weighting module is introduced to reduce the area of conventional ladder capacitors; and a redundant array-assisted Analog-to-Digital Converter (ADC) is proposed to improve linearity during ADC quantization. The proposed architecture can achieve multi-bit multiplication and accumulation (MAC), OR accumulation (ORA), and XNOR accumulation (XNORA). Simulated using a 28-nm CMOS process, the architecture demonstrated a minor standard deviation in BL voltage of 16.27 mV at the SS process corner, as evidenced by Monte Carlo simulation. At the TT process corner, the energy expenditure for MAC, XNORA, and ORA operations was 5.76, 5.85, and 5.82 fJ/op, respectively.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142148723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An energy-efficient 16 MS/s 10-bit SAR ADC with MSB-block switching scheme 采用 MSB 块切换方案的高能效 16 MS/s 10 位 SAR ADC
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-09-02 DOI: 10.1016/j.mejo.2024.106369
{"title":"An energy-efficient 16 MS/s 10-bit SAR ADC with MSB-block switching scheme","authors":"","doi":"10.1016/j.mejo.2024.106369","DOIUrl":"10.1016/j.mejo.2024.106369","url":null,"abstract":"<div><p>An energy-efficient MSB-block switching scheme without common-mode voltage variation for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. Benefit from a pair of extra switches embedded in the capacitive digital-to-analog converter (CDAC), the proposed MSB-block switching scheme can reduce switching energy without further reducing the capacitor unit. The proposed switching scheme can achieve 93.8 % and 49.9 % savings in switching energy compared with the conventional switching scheme and the Vcm-based switching scheme, and the simulated differential-nonlinearity (DNL) and integrated-nonlinearity (INL) are 0.160 and 0.156LSB, respectively. The proposed switching scheme is verified in a 1.2-V 10-bit 16 MS/s SAR ADC in 65 nm CMOS technology. At maximum sampling rate, the proposed SAR ADC achieves an effective number of bits (ENOB) of 9.50 and a power consumption of <span><math><mrow><mn>103.5</mn><mi>μ</mi><mi>W</mi></mrow></math></span>, leading to a Figure of Merit of 8.93 fJ/Conversion-step.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142157470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effects of NiO doping and trench wall tilt on Ga2O3 PiN diodes performance 氧化镍掺杂和沟道壁倾斜对 Ga2O3 PiN 二极管性能的影响
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-09-02 DOI: 10.1016/j.mejo.2024.106399
{"title":"Effects of NiO doping and trench wall tilt on Ga2O3 PiN diodes performance","authors":"","doi":"10.1016/j.mejo.2024.106399","DOIUrl":"10.1016/j.mejo.2024.106399","url":null,"abstract":"<div><p>Gallium Oxide (Ga<sub>2</sub>O<sub>3</sub>) is a promising material for next-generation power semiconductors due to its wide bandgap (∼4.9 eV), high Baliga's figure of merit (FOM) (3444 W/cmK), and high breakdown field (E<sub><em>c</em></sub>, 8 MV/cm). To achieve high blocking and low leakage current, research has been conducted on PN heterojunctions and bevel structures. In this paper, we performed simulations using Sentaurus TCAD to investigate the impact of NiO doping concentration and NiO's trench tilt angle on the electrical characteristics of NiO/Ga<sub>2</sub>O<sub>3</sub> PiN diodes with trench NiO. As the NiO doping concentration increased, the resistance decreased from 21.5 to 7.5 mΩcm<sup>2</sup>, and we observed the expansion of depletion from NiO to the NiO/Ga<sub>2</sub>O<sub>3</sub> interface. Furthermore, we confirmed a reduction in resistance and a change in breakdown voltage with an increase in NiO trench tilt. By understanding the optimal angle to mitigate the concentration of high electric fields in the edge region, we anticipate the fabrication of stable Ga<sub>2</sub>O<sub>3</sub> PiN diodes.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142229126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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