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A fast LMS-based digital background calibration technique for 16-bit SAR ADC with modified shuffling scheme
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106547
Jiacong Wang , Biyun Du , Zhangjie Su , Ke Hu , Jia Yu , Chao Cao , Shubin Liu , Haijun Guo
{"title":"A fast LMS-based digital background calibration technique for 16-bit SAR ADC with modified shuffling scheme","authors":"Jiacong Wang ,&nbsp;Biyun Du ,&nbsp;Zhangjie Su ,&nbsp;Ke Hu ,&nbsp;Jia Yu ,&nbsp;Chao Cao ,&nbsp;Shubin Liu ,&nbsp;Haijun Guo","doi":"10.1016/j.mejo.2024.106547","DOIUrl":"10.1016/j.mejo.2024.106547","url":null,"abstract":"<div><div>-This paper introduces a modified shuffling scheme to achieve less overhead in ADC, lower power consumption for digital calibration and higher update frequency. Different-size unit capacitors are used in the shuffling, which reduces the number of switches and capacitors by almost half while remaining complexity of the digital circuit unchanged. Additionally, a novel LMS-based digital background calibration technique suitable for split-based ADC is proposed. Fast convergence and linear calibration are achieved with the improved gradient descent algorithm, which uses Momentum and Nesterov accelerated gradient (NAG). The convergence speed is found to be over 10 times faster than typical LMS algorithm and maintain calibration accuracy in MATLAB simulation of a 16-bit, 1 MS/s SAR ADC.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106547"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143162388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Stacked gate-all-around nanosheet transistors with full-air-spacers for reducing parasitic capacitance to improve device and circuit performance
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106535
Lianlian Li , Lei Cao , Xuexiang Zhang , Qingkun Li , Zhenhua Wu , Meihe Zhang , Yunjiao Bao , Peng Wang , Renjie Jiang , Anyan Du , Qingzhu Zhang , Huaxiang Yin
{"title":"Stacked gate-all-around nanosheet transistors with full-air-spacers for reducing parasitic capacitance to improve device and circuit performance","authors":"Lianlian Li ,&nbsp;Lei Cao ,&nbsp;Xuexiang Zhang ,&nbsp;Qingkun Li ,&nbsp;Zhenhua Wu ,&nbsp;Meihe Zhang ,&nbsp;Yunjiao Bao ,&nbsp;Peng Wang ,&nbsp;Renjie Jiang ,&nbsp;Anyan Du ,&nbsp;Qingzhu Zhang ,&nbsp;Huaxiang Yin","doi":"10.1016/j.mejo.2024.106535","DOIUrl":"10.1016/j.mejo.2024.106535","url":null,"abstract":"<div><div>In this paper, we propose a full-air-spacers (FAS, air spacers and air inner spacers) technique and a feasible fabrication approach on gate all around (GAA) nanosheet field-effect-transistors (NSFETs) by a backside selective etching (BSE). Compared with NSFETs with SiN<sub>x</sub> spacers and low-κ spacers, the FAS NSFETs exhibit no obvious degradation in DC characteristics, but show enormous improvements in AC characteristics and circuit benefits. The FAS technology provides 79.40 % reduction in effective capacitance and 75.71 % reduction in intrinsic delay. Moreover, the power consumption is reduced by 60.84 % at the same frequency, while the frequency gain is increased by 87.50 % at the same power consumption on the 17-stage ring oscillators (ROs). In addition, the FAS NSFETs-based 6T static random memories (SRAMs) cell has achieved 44.26 % and 82.46 % decrease in read time and write time, while 8.40 % and 4.54 % improvement in read noise tolerance and write noise tolerance, compared to the SiN<sub>x</sub>-NSFETs-based 6T-SRAM cell.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106535"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143162389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A DTC-based fractional-N ADPLL using dual-core noise circulating DCO and loop bandwidth control techniques
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106525
Jun Xu , Changchun Zhang , Yi Zhang , Jing Wang
{"title":"A DTC-based fractional-N ADPLL using dual-core noise circulating DCO and loop bandwidth control techniques","authors":"Jun Xu ,&nbsp;Changchun Zhang ,&nbsp;Yi Zhang ,&nbsp;Jing Wang","doi":"10.1016/j.mejo.2024.106525","DOIUrl":"10.1016/j.mejo.2024.106525","url":null,"abstract":"<div><div>A fractional-N all digital phase locked loop (ADPLL) frequency synthesizer using loop bandwidth control technique is proposed in 65 nm CMOS. A lock detector gradually adjusts the loop bandwidth according to the state of the ADPLL to speed up the locking process and finally achieves accurate lock. A delta-sigma modulator (DSM) quantization noise cancellation technique which is based on a digital-to-time converter (DTC) is utilized to achieve lower fractional spurs, and a dual-core noise circulating digital controlled oscillator (DCO) is presented to achieve lower phase noise. According to the post-layout simulation results, the proposed ADPLL can operate properly at the frequency range of 12.0–15.0 GHz, with integrated jitter of 739 fs, reference spur of −80.3 dBc, fractional spur of −52.3 dBc, and power consumption of 36 mW.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106525"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143163163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An 89-dB SNDR 50-kHz BW CT ZOOM ADC employing FIR DAC to enhance the ADC linearity
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106526
Shida Song, Yuhua Liang
{"title":"An 89-dB SNDR 50-kHz BW CT ZOOM ADC employing FIR DAC to enhance the ADC linearity","authors":"Shida Song,&nbsp;Yuhua Liang","doi":"10.1016/j.mejo.2024.106526","DOIUrl":"10.1016/j.mejo.2024.106526","url":null,"abstract":"<div><div>This paper presents a CT Zoom ADC using a single-bit quantized first-order Sigma-Delta ADC as the coarse quantization ADC. The coarse quantization output is converted to be a multi-level output through a FIR filter, enhancing the ADC linearity and suppressing the sensitivity to clock jitter. Thus, not only can the designing difficulty be relieved, the power efficiency can be also improved. The fine-grained ADC adopts a third-order Sigma Delta ADC with single-bit quantization. The final output of the ZOOM ADC is the weighted average sum of the two-stage outputs.</div><div>In a 0.18 μm CMOS process, the circuit has achieved good performance. Within a bandwidth of 50 kHz, it achieves 89.3 dB SNDR, 14.5bits ENOB. The ADC core consumes 380 μW at a 1.8-V supply, resulting in a SNDR-based FoM of 170.5 dB. The size of the core ADC is 380μm × 520 μm.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106526"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143163167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A fully-integrated VCO-based analog-assisted-digital low-dropout regulator with feed-forward PSR enhancement for energy-harvesting wireless sensor node
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106322
Zhenglai Wang , Bo Zhao , Jianming Zhao , Yuxuan Luo
{"title":"A fully-integrated VCO-based analog-assisted-digital low-dropout regulator with feed-forward PSR enhancement for energy-harvesting wireless sensor node","authors":"Zhenglai Wang ,&nbsp;Bo Zhao ,&nbsp;Jianming Zhao ,&nbsp;Yuxuan Luo","doi":"10.1016/j.mejo.2024.106322","DOIUrl":"10.1016/j.mejo.2024.106322","url":null,"abstract":"<div><div>The sensor nodes within wireless sensor networks (WSNs) can harvest energy from the environment to supplement their power needs. The sensor node requires a low-voltage regulator to condition the weak and unstable harvested energy. This paper presents a self-clocked fully-integrated feedforward-biased hybrid low-dropout regulator (FFB-HLDO) with a dual differential VCO (DD-VCO) pair for WSN sensor applications. The proposed HLDO is fully integrated without load capacitor. To enhance the Power Supply Rejection (PSR) performance, an analog feedforward biased (AFFB) technique is proposed to reduce supply ripples. Besides, a distortion module (DM) is proposed to improve the transient response. Implemented in a 65 nm CMOS technology, this capacitor-less and self-clocked HLDO can provide the minimum output of 0.3V and the maximum output of 1.5V from 0.55–1.6V input, and the area is 0.0123 mm<sup>2</sup>. For the maximum load current of 0.26 mA, the peak current efficiency is 98.9%. With a quiescent current of 300 nA, the frequency of 0-dB-PSR is 100 MHz.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106322"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143162265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A sub-6 GHz and millimeter-wave IPD tri-band bandpass filter chip with wide stopband, high roll-off, and enhanced bandwidth
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106527
Yuxin Liu , Yongle Wu , Shuchen Zhen , Yuhao Yang , Weimin Wang , Qinghua Yang
{"title":"A sub-6 GHz and millimeter-wave IPD tri-band bandpass filter chip with wide stopband, high roll-off, and enhanced bandwidth","authors":"Yuxin Liu ,&nbsp;Yongle Wu ,&nbsp;Shuchen Zhen ,&nbsp;Yuhao Yang ,&nbsp;Weimin Wang ,&nbsp;Qinghua Yang","doi":"10.1016/j.mejo.2024.106527","DOIUrl":"10.1016/j.mejo.2024.106527","url":null,"abstract":"<div><div>In this paper, a sub-6 GHz and millimeter-wave tri-band bandpass filter (T-BPF) is proposed. The first passband is at FR1 (450 MHz-6.0 GHz), and the other two are at FR2 (24.25 GHz–52.6 GHz), respectively. The high-frequency part is a stepped-impedance coupled-line dual-band filter. The low-frequency part is a low-order filter with single transmission zero (TZ), showing poor roll-off on the side without a TZ. However, under the influence of the high-frequency part, it generates an extra TZ on the left side of the low-frequency passband, improving the passband's roll-off. For demonstration, based on GaAs integrated passive device (IPD) technology, a T-BPF operating at 4.3/24.7/39.4 GHz is designed, fabricated, and measured. The size of the T-BPF is only 1.64 mm ∗ 1.61 mm. The measured results show that the filter realizes insertion losses (ILs) of 1.29/2.67/1.77 dB, return losses (RLs) of 24/21/20 dB at center frequencies, good roll-off, and wide stopband from 6.3 (28.1) GHz to 22.4 (35.2) GHz.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106527"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143163166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 32-channels analog multiplexer with crosstalk compensation technique in 45 nm CMOS
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106496
Jie Wu, Qiao Meng, Gaojing Li, Sha Li, Shaocong Guo, Yujia Huang
{"title":"A 32-channels analog multiplexer with crosstalk compensation technique in 45 nm CMOS","authors":"Jie Wu,&nbsp;Qiao Meng,&nbsp;Gaojing Li,&nbsp;Sha Li,&nbsp;Shaocong Guo,&nbsp;Yujia Huang","doi":"10.1016/j.mejo.2024.106496","DOIUrl":"10.1016/j.mejo.2024.106496","url":null,"abstract":"<div><div>This paper presents a multiplexer that is capable of modulating 32-channels analog signal, which is a promising approach to simplify transmission system. An 8-channels prototype multiplexer with integral functionality and non-ideal factors is fabricated in 45 nm CMOS with area of 0.59 mm<sup>2</sup>, and verified in a QAM-256 system with 1.2V supply. The proposed multiplexer employs a semi-tree structure to achieve compromise between scale and speed. To relieve adverse effect caused by crosstalk between channels, the auxiliary reset compensation circuit combined with a dedicated timing sequence is utilized. Additionally, the proposed high-speed gate voltage bootstrap switch and high-bandwidth input buffer ensure that the signal remains linear during transmission. In the experimental result, the multiplexer can achieve a pulse width of at least 77ps in 8Gbps code rate, and the root mean square error due to nonlinearity between differential input and output is 1.869 %. The error vector magnitude (EVM) obtained by analyzing output versus input of multiplexer is less than 1.413 %.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106496"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143163322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A cross-scale investigation on transient electrothermal performance for power MOSFETs at device-package level
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2025.106561
Yuxuan Dai , Jiafei Yao , Jing Chen , Maolin Zhang , Yucheng Xu , Qing Yao , Qingyou Qian , Jun Zhang , Kemeng Yang , Yufeng Guo
{"title":"A cross-scale investigation on transient electrothermal performance for power MOSFETs at device-package level","authors":"Yuxuan Dai ,&nbsp;Jiafei Yao ,&nbsp;Jing Chen ,&nbsp;Maolin Zhang ,&nbsp;Yucheng Xu ,&nbsp;Qing Yao ,&nbsp;Qingyou Qian ,&nbsp;Jun Zhang ,&nbsp;Kemeng Yang ,&nbsp;Yufeng Guo","doi":"10.1016/j.mejo.2025.106561","DOIUrl":"10.1016/j.mejo.2025.106561","url":null,"abstract":"<div><div>This article proposes a fully automated cross-scale relaxation scheme for analyzing the temporal electrothermal behavior of power MOSFETs, spanning from the complete micrometer-scale devices to the millimeter-scale packages. The presented scheme integrates the device-level technology computer-aided design (TCAD) simulator Silvaco with the package-level finite element analysis (FEA) simulator ANSYS Icepak, achieving self-consistent electrothermal effects. It reduces data transfer time between the simulators while harnessing their complementary strengths to address complex device structures, package structures, and heat flow environments. Simulation results are then compared with alternative methods, and their distinct features are analyzed in detail. Furthermore, empirical models are derived to characterize electrothermal parameters and extract the thermal time constant. The method's effectiveness is validated using a commercial power MOSFET with TO-220F packaging. The simulations, models, and experiments produced highly satisfactory fits, enabling an effective way for device-package-level co-design and rapid determination of thermal time constant.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106561"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143163324","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel dual-band power amplifier with integrated harmonic control based on dual transmission lines
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2025.106552
Jindong Zhang, Cuiping Yu, Hao Li, Yuanan Liu
{"title":"A novel dual-band power amplifier with integrated harmonic control based on dual transmission lines","authors":"Jindong Zhang,&nbsp;Cuiping Yu,&nbsp;Hao Li,&nbsp;Yuanan Liu","doi":"10.1016/j.mejo.2025.106552","DOIUrl":"10.1016/j.mejo.2025.106552","url":null,"abstract":"<div><div>In this paper, a novel and effective design method for dual-band matching is proposed based on a dual transmission line structure. Compared to conventional design methods, in which the fundamental matching network as well as the harmonic control network are designed separately, the proposed method integrates the harmonic control network into the fundamental matching network, thus simplifying the design and facilitating analytical calculations and accurate matching. For validation, a dual-band power amplifier (PA) is designed and fabricated by using CG2H40010F GaN HEMT. Measurements indicate that the designed PA can deliver saturated output power of 41.5 and 41.4 dBm at 2.6 and 3.5 GHz, respectively. The drain efficiency is 60.2 %–71.8 % at 2.43–2.79 GHz and 60.1 %–70.1 % at 3.40–3.57 GHz. Digital predistortion (DPD) testing was conducted using 20 MHz and 100 MHz 5G NR signals, achieving adjacent channel leakage ratios (ACLR) better than −48 dBc with DPD. Excellent linearity was demonstrated across both frequency bands.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106552"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143163327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 4.5-MS/s 12-bit Vcm self-generated SAR ADC in 130-nm CMOS
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-02-01 DOI: 10.1016/j.mejo.2024.106548
Dun Yan , Xin Zhang , Yu Xiao , Xiaoyou Yu , Shaoliang Peng , Songting Li , Kai Tang , Jie Liu
{"title":"A 4.5-MS/s 12-bit Vcm self-generated SAR ADC in 130-nm CMOS","authors":"Dun Yan ,&nbsp;Xin Zhang ,&nbsp;Yu Xiao ,&nbsp;Xiaoyou Yu ,&nbsp;Shaoliang Peng ,&nbsp;Songting Li ,&nbsp;Kai Tang ,&nbsp;Jie Liu","doi":"10.1016/j.mejo.2024.106548","DOIUrl":"10.1016/j.mejo.2024.106548","url":null,"abstract":"<div><div>This paper presents a 12-bit, 4.5 MS/s synchronous SAR ADC implemented in SMIC's 130-nm CMOS technology. It features a novel method for internal common-mode (<em>V</em><sub><em>cm</em></sub>) generation via introduces switched-capacitor technique, eliminating the need for external <em>V</em><sub><em>cm</em></sub> generation circuitry and reducing parasitics. To enhance capacitor matching and mitigate mismatch, thermometer encoding is employed for the most significant 6-bit of the ADC. The comparator boasts a dynamic pre-amplifier with switching capacitance tail current for improved signal amplification. The ADC exhibits excellent linearity with DNL of +0.59/−0.57 LSB and INL of +1.02/−1.12 LSB. Occupying a core area of 0.144 mm<sup>2</sup>, it achieves SNDR of 69.63 dB, ENOB of 11.27-bit, SFDR of 78.17 dB, and THD of −76.33 dB. Operating at 3.3 V, it consumes 2.577 mW with FoM<sub>W</sub> of 231.9 fJ/conversion-step. These measurement results confirm the feasibility and effectiveness of the proposed <em>V</em><sub><em>cm</em></sub> self-generation approach, offering fresh insights into <em>V</em><sub><em>cm</em></sub> generation in ADC design, with potential implications for future ADC architectures.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"156 ","pages":"Article 106548"},"PeriodicalIF":1.9,"publicationDate":"2025-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143162391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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