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An 8-bit 1.16 mw 500 ms/s SAR ADC with bidirectional-bit-distribution-based offset calibration and partially activated accelerating current source
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-03-24 DOI: 10.1016/j.mejo.2025.106649
Min Lin, Pengjun He, Jinpeng Tian
{"title":"An 8-bit 1.16 mw 500 ms/s SAR ADC with bidirectional-bit-distribution-based offset calibration and partially activated accelerating current source","authors":"Min Lin,&nbsp;Pengjun He,&nbsp;Jinpeng Tian","doi":"10.1016/j.mejo.2025.106649","DOIUrl":"10.1016/j.mejo.2025.106649","url":null,"abstract":"<div><div>This paper presents an 8-bit 500MS/s single-channel Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). It features: 1) a fast-converging bidirectional-bit-distribution-based (BBDB) ping-pong comparator calibration, which bidirectionally adjusts the offset of the two comparators to their mean values, and reduces the offset standard deviation to 0.707 times initial offset value; and 2) the use of partially activated accelerating current source (ACS), depending on the operating state of the SAR ADC. When ACS is enabled, it reduces the single-bit decision time of the comparator by at least 14%. The prototype ADC, implemented in a 40 nm Low-Leakage CMOS process, achieves post simulated SNDR and SFDR of 47.4 dB and 65.7 dB, respectively, at Nyquist frequency input. Operating at a 1.1 V single supply, the ADC consumes 1.16 mW, leading to the Walden figure of merit (FoMw) of 12.2 fJ/conv-step.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106649"},"PeriodicalIF":1.9,"publicationDate":"2025-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 500 MS/s 12b single channel SAR-assisted pipelined ADC with two-stage open-loop dynamic amplifier
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-03-22 DOI: 10.1016/j.mejo.2025.106659
Qing Su , Xuan Guo , Hanbo Jia , Heping Ma , Linzhen Wu , Kai Sun , Xinyu Liu
{"title":"A 500 MS/s 12b single channel SAR-assisted pipelined ADC with two-stage open-loop dynamic amplifier","authors":"Qing Su ,&nbsp;Xuan Guo ,&nbsp;Hanbo Jia ,&nbsp;Heping Ma ,&nbsp;Linzhen Wu ,&nbsp;Kai Sun ,&nbsp;Xinyu Liu","doi":"10.1016/j.mejo.2025.106659","DOIUrl":"10.1016/j.mejo.2025.106659","url":null,"abstract":"<div><div>—This work presents a single-channel, fully-dynamic SAR-assisted pipelined ADC that performs well over wide bandwidth. The ADC employs a dynamic, open-loop, two-stage cascade amplifier to realize 32x high-gain with efficient power. Meanwhile, the amplifier adopts strong output drive to reduce amplification time and still keeps good linearity. A parasitic optimized bootstrap switch is employed to enhance linearity for S/H at high speeds. It has also been explored several methods to shorten the turn-on paths of bootstrap switch in both schematic and layout. The prototype ADC was fabricated in a 28-nm process, it consumes 5.1-mW from 1V supply at 500 MS/s and occupies an area of 0.011-mm<sup>2</sup>. For 43.80 MHz input, the ADC achieves a SNDR of 58.2 dB and a SFDR of 71.9 dBc. With Nyquist input of 236.33 MHz, the measured SNDR and SFDR can have good performance of 56.3 dB and 69.4 dBc. This leads to a Schreier and a Walden figure-of-merit (FoM) values of 165.1 dB and 16.18 fJ/conv.-step, respectively.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"160 ","pages":"Article 106659"},"PeriodicalIF":1.9,"publicationDate":"2025-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143768637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A digital background calibration method for SAR ADC based on dual-layer feedforward neural network
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-03-22 DOI: 10.1016/j.mejo.2025.106645
Tiehu Li , Jintao Huang , Jun Zeng , Chaodong Guo , Wei Zhang , Xiaojun Fu , Daiguo Xu , Gang Yan , Junyi Jiang , Rui Lai , Jun-an Zhang
{"title":"A digital background calibration method for SAR ADC based on dual-layer feedforward neural network","authors":"Tiehu Li ,&nbsp;Jintao Huang ,&nbsp;Jun Zeng ,&nbsp;Chaodong Guo ,&nbsp;Wei Zhang ,&nbsp;Xiaojun Fu ,&nbsp;Daiguo Xu ,&nbsp;Gang Yan ,&nbsp;Junyi Jiang ,&nbsp;Rui Lai ,&nbsp;Jun-an Zhang","doi":"10.1016/j.mejo.2025.106645","DOIUrl":"10.1016/j.mejo.2025.106645","url":null,"abstract":"<div><div>This paper addresses the impact of capacitor mismatch, comparator offset, and incomplete settling of the digital-to-analog converter (DAC) on the dynamic performance of Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs). A digital background calibration method using a double-layer feedforward neural network is proposed. The network is trained in MATLAB and implemented on an FPGA to validate the calibration algorithm. The study explores the influence of parameters like the number of neurons, training samples, and iterations on performance. FPGA results show that, after calibration, the Spurious-Free Dynamic Range (SFDR) and Signal-to-Noise-and-Distortion Ratio (SNDR) of a 12-bit 100 MSPS SAR ADC model improved from 46.58 dB and 46.53 dB to 98.10 dB and 70.87 dB. Similarly, for a 10-bit 31.25 MSPS SAR ADC chip, SFDR and SNDR increased from 61.46 dB and 46.86 dB to 79.87 dB and 57.09 dB. These results confirm the proposed method’s effectiveness for addressing non-idealities in both simulated models and hardware.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106645"},"PeriodicalIF":1.9,"publicationDate":"2025-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143705554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A dual-channel half-rate 32 Gb/s, 5.3 pJ/bit SerDes transceiver with 3-tap-FFE and CTLE in 28-nm CMOS for very short reach C2C and C2M interconnection
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-03-21 DOI: 10.1016/j.mejo.2025.106641
Zhaoyang Liu , Zhanhao Wen , Bao Chen , Jiang Xu , Zedong Wang , Xuqiang Zheng
{"title":"A dual-channel half-rate 32 Gb/s, 5.3 pJ/bit SerDes transceiver with 3-tap-FFE and CTLE in 28-nm CMOS for very short reach C2C and C2M interconnection","authors":"Zhaoyang Liu ,&nbsp;Zhanhao Wen ,&nbsp;Bao Chen ,&nbsp;Jiang Xu ,&nbsp;Zedong Wang ,&nbsp;Xuqiang Zheng","doi":"10.1016/j.mejo.2025.106641","DOIUrl":"10.1016/j.mejo.2025.106641","url":null,"abstract":"<div><div>This paper proposes a dual-channel very short reach (VSR) SerDes transceiver designed for chip-to-chip (C2C) or chip-to-module (C2M) interconnections. The transmitter utilizes a half-rate architecture and is composed of high-speed multiplexers (MUXs), a clock distribution module, and an adjustable 3-tap feed-forward equalizer (FFE). The proposed receiver employs a half-rate oversampling architecture, consisting of a continuous time linear equalizer (CTLE), a CML-based static comparator, high-speed demultiplexers (DEMUXs), a multiphase clock generation module based on an active polyphase filter (APFF), a phase interpolator (PI), and a clock and data recovery (CDR) loop. This dual-channel transceiver is designed with a 28-nm CMOS process technology and supplied with 1/1.2 V. Post-simulation results show that this transceiver can operate at a data rate of 32 Gb/s with a power efficiency of 1.81 pJ/bit for transmitter and 3.5 pJ/bit for receiver. The transceiver’s BER is less than 1E-12 and eye-wide-opening is 0.86 UI, which is under 12.4 dB channel loss at 16 GHz Nyquist frequency.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106641"},"PeriodicalIF":1.9,"publicationDate":"2025-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143686133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 107.5-dB dynamic range 402-μW event-driven dynamic zoom ADC with voice activity detection function for audio applications
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-03-19 DOI: 10.1016/j.mejo.2025.106654
Zhiming Li , Lei Dong , Quan Sun , Yang Chen , Yuming Li , Jie Zhang , Huanhuan Qi , Xiaofei Wang , Hong Zhang
{"title":"A 107.5-dB dynamic range 402-μW event-driven dynamic zoom ADC with voice activity detection function for audio applications","authors":"Zhiming Li ,&nbsp;Lei Dong ,&nbsp;Quan Sun ,&nbsp;Yang Chen ,&nbsp;Yuming Li ,&nbsp;Jie Zhang ,&nbsp;Huanhuan Qi ,&nbsp;Xiaofei Wang ,&nbsp;Hong Zhang","doi":"10.1016/j.mejo.2025.106654","DOIUrl":"10.1016/j.mejo.2025.106654","url":null,"abstract":"<div><div>This paper presents a dynamic zoom analog-to-digital converter (ADC) for audio applications, which combines a 5-bit coarse event-driven (ED) ADC (also called level-crossing ADC) and a 3rd-order, single-bit discrete-time ΔΣ modulator (ΔΣM). With 2 low-power continuous-time (CT) comparators and a corresponding digital circuit operating only at the event that the input signal crosses the reference levels, the coarse ED ADC consumes much less power than those coarse SAR ADCs operating under the sampling frequency (Fs) in the conventional dynamic zoom ADC schemes, because the ED scheme operates with much less activity and shows higher adaptivity to real acoustic signal applications. Moreover, the ED ADC output can be utilized to generate a voice activity detection (VAD) signal, which provides a simple on-device audio computing function for the analog front-ends in audio applications. A cascoded floating-inverter-amplifier (FIA) based integrator is employed in the fine ΔΣM to reduce power consumption further. Fabricated in a 0.18-μm CMOS process, the prototype ADC chip achieves 102.1-dB peak signal-to-noise ratio (SNR), 103.1-dB peak signal-to-noise-and-distortion ratio (SNDR), and 107.5-dB dynamic range (DR) for a 24-kHz bandwidth and 6.144-MHz Fs, while consuming only 402 μW under the 1.8-V power supply, resulting in a Schreier Figure-of-Merit (FoMs) of 185.3 dB.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106654"},"PeriodicalIF":1.9,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143685621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of a dual-band filter based on mode composite structure combining substrate integrated waveguides and slotlines
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-03-19 DOI: 10.1016/j.mejo.2025.106650
Yuhao Yang , Yongle Wu , Weimin Wang , Shiyu Xie , Yuanan Liu
{"title":"Design of a dual-band filter based on mode composite structure combining substrate integrated waveguides and slotlines","authors":"Yuhao Yang ,&nbsp;Yongle Wu ,&nbsp;Weimin Wang ,&nbsp;Shiyu Xie ,&nbsp;Yuanan Liu","doi":"10.1016/j.mejo.2025.106650","DOIUrl":"10.1016/j.mejo.2025.106650","url":null,"abstract":"<div><div>This paper proposes a novel mode composite structure that combines substrate integrated waveguides (SIWs) and slotlines, offering a compact solution for a dual-band filter targeting both microwave and millimeter-wave bands. The TEM mode of slotlines and TE modes of SIWs within a single substrate layer are transmitted simultaneously. They can share ports, feeding circuits and feeding apertures, which means the proposed structure is compact, offering efficient integration. Particularly, slotlines embedded are capable of generating low-frequency resonances with feeding circuits, and are able to regulate the field distributions of TE modes in high bands. The performance of the filter is validated through simulation and measurement, demonstrating bandwidths from 15.49 GHz to 17.42 GHz and from 33.05 GHz to 35.10 GHz, with excellent out-of-band rejection more than 20.24 dB. It is suitable for Ku and Ka applications.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106650"},"PeriodicalIF":1.9,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143686068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Compact HRS IPD N77 bandpass filter based on tapered spiral inductors and innovative source-load coupling
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-03-19 DOI: 10.1016/j.mejo.2025.106653
Yuhan Cao, Bukun Xu, Bo Yuan, Gaofeng Wang
{"title":"Compact HRS IPD N77 bandpass filter based on tapered spiral inductors and innovative source-load coupling","authors":"Yuhan Cao,&nbsp;Bukun Xu,&nbsp;Bo Yuan,&nbsp;Gaofeng Wang","doi":"10.1016/j.mejo.2025.106653","DOIUrl":"10.1016/j.mejo.2025.106653","url":null,"abstract":"<div><div>A compact bandpass filter (BPF) has been developed and fabricated using high-resistivity silicon (HRS) integrated passive device (IPD) technology. The core component of the BPF is designed with a source-load coupling network, which facilitates the generation of transmission zeros on both sides of the passband. To improve high-frequency stopband rejection and ensure impedance matching between the source-load coupling network and the load, a cascaded lumped Pi-type network has been integrated into the design. The layout of the design employs high-Q tapered spiral inductors, which are utilized to minimize insertion loss. To evaluate the performance of the design, an on-chip filter operating within the 5G N77 band has been fabricated, achieving compact dimensions of 1 × 0.5 mm<sup>2</sup>. Measurement results indicate that the BPF attains an N77 in-band insertion loss of less than 1.7 dB and a 3-dB fractional bandwidth exceeding 61.3 %, along with an out-of-band rejection of 23.4 dB at the LTE band 3 uplink frequency.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106653"},"PeriodicalIF":1.9,"publicationDate":"2025-03-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143685620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A PVT-Insensitive instrumentation amplifier with 17.95 mHz high-pass corner based on a PSSP hybrid feedback resistor
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-03-18 DOI: 10.1016/j.mejo.2025.106640
Hao Xu, Shilong Chen, Lu Liu, Guangyin Shi, Tianke Li, Zhiqiang Li, Jun Zhang, Haiying Zhang
{"title":"A PVT-Insensitive instrumentation amplifier with 17.95 mHz high-pass corner based on a PSSP hybrid feedback resistor","authors":"Hao Xu,&nbsp;Shilong Chen,&nbsp;Lu Liu,&nbsp;Guangyin Shi,&nbsp;Tianke Li,&nbsp;Zhiqiang Li,&nbsp;Jun Zhang,&nbsp;Haiying Zhang","doi":"10.1016/j.mejo.2025.106640","DOIUrl":"10.1016/j.mejo.2025.106640","url":null,"abstract":"<div><div>This work presents a capacitively coupled instrumentation amplifier (IA) for applications in the field of physiological signals, and the proposed hybrid resistor realizes its feedback resistance. It allows the capacitively coupled IA to achieve Tera-ohm (T<span><math><mi>Ω</mi></math></span>) feedback resistance and be robust to process, voltage, and temperature (PVT) variations. This hybrid feedback resistor and feedback capacitor of the capacitively coupled IA form a low-pass filter to filter out undesired spike signals. The capacitively coupled IA was implemented in a 130 nm standard CMOS process. The simulation results show that the proposed capacitively coupled IA can realize a high-pass corner of 17.95 mHz and a gain of 36.69 dB. The difference between the maximum and minimum values of the high-pass corner of the capacitively coupled IA under different PVT conditions is only 0.014 Hz. The maximum value of the absolute value of its high-pass corner change rate is 0.30. The proposed capacitively coupled IA can realize a 72.6 dB signal-to-noise and distortion ratio (SNDR).</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106640"},"PeriodicalIF":1.9,"publicationDate":"2025-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143686092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 257-nA quiescent current 200-mA load low-dropout regulator with reference sampling technique and loop reconfigurable technique
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-03-17 DOI: 10.1016/j.mejo.2025.106648
Shangzheng Yang, Kefan Qin, Xiang Yan, Haitao Cui, Jianwei Zhao, Wei Ma, Weibo Hu, Member, IEEE
{"title":"A 257-nA quiescent current 200-mA load low-dropout regulator with reference sampling technique and loop reconfigurable technique","authors":"Shangzheng Yang,&nbsp;Kefan Qin,&nbsp;Xiang Yan,&nbsp;Haitao Cui,&nbsp;Jianwei Zhao,&nbsp;Wei Ma,&nbsp;Weibo Hu,&nbsp;Member, IEEE","doi":"10.1016/j.mejo.2025.106648","DOIUrl":"10.1016/j.mejo.2025.106648","url":null,"abstract":"<div><div>This paper proposes an ultra-low quiescent current low-dropout regulator (LDO) for Internet-of-Things and portable devices. To reduce power consumption in the reference, the conventional continuous-on reference is replaced by intermittent-on reference, and using switching capacitors to store reference voltage, which called reference sampling technique (RST). Meanwhile, to decrease the quiescent current in LDO main loop, the loop reconfigurable technique (LRT) is implemented. When the LDO with no load, the main loop is two-stage structure with small power transistor, which results in low quiescent current. When a heavy load is added, the main loop is changed into a three-stage structure with large power transistor. A prototype chip is fabricated in 0.35 μm CMOS process, occupying 0.6 mm<sup>2</sup> area and consumes 257 nA quiescent current. Furthermore, owing to the transient enhance circuit, when the load current jumps from 0 mA to 200 mA within 1 μS, the output settling time is about 10 μS, with an undershoot voltage of 160 mV.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106648"},"PeriodicalIF":1.9,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143705555","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
X-parameters modeling based on LSTM and CG-BPNN for transistor
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-03-17 DOI: 10.1016/j.mejo.2025.106646
Shu-yue Yang , Qian Lin , Hai-feng Wu
{"title":"X-parameters modeling based on LSTM and CG-BPNN for transistor","authors":"Shu-yue Yang ,&nbsp;Qian Lin ,&nbsp;Hai-feng Wu","doi":"10.1016/j.mejo.2025.106646","DOIUrl":"10.1016/j.mejo.2025.106646","url":null,"abstract":"<div><div>In order to reduce the time of device parameter measurement or simulation and improve the efficiency of circuit design, X-parameters of gallium nitride high electron mobility transistor (GaN HEMT) are modeled based on long short term memory (LSTM) and double hidden layer conjugate gradient back propagation neural network (CG-BPNN) in this paper. Then, to verify the modeling efficiency of the two models, the harmonic balance experiments are carried out to obtain the three harmonics of the predicted data and expected data. Finally, the three harmonic errors of LSTM model are 0.801, 7.511 and 13.470 dBm, respectively, and the three harmonic errors of double hidden layer CG-BPNN model are 0.1117, 2.594 and 3.423 dBm, respectively. Through the above experiments, it is proved that double hidden layer CG-BPNN model proposed here can effectively model GaN HEMT with large-signal. The application in engineering is the demonstration of superior performance of the proposed CG-BPNN model in terms of accurate representation of X-parameters for transistor.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106646"},"PeriodicalIF":1.9,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143739765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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