A new double-trench gate 4H-SiC LDMOS with heterojunction and buffer layer for improved single-event burnout tolerance

As an important aerospace power device, silicon carbide (SiC) Lateral Diffused Metal Oxide Semiconductor (LDMOS) is susceptible to single-event burnout (SEB), which causes catastrophic damage when exposed to space radiation. The current work employs the Sentaurus TCAD simulations to present the SEB hardening method for a 1.2-kV 4H-SiC LDMOS. A double-trench gate 4H-SiC LDMOS containing low specific on-resistance ($R_{on,sp}$) is proposed, significantly improving the device’s SEB threshold voltage ($V_{SEB}$). The proposed hardening design integrates multi-buffer layer with a heterojunction, impressively mitigating the high electric field at the drain area while suppressing the parasitic bipolar junction transistor (BJT). Besides, the device’s resistance is significantly decreased by designing the double-trench gate and current spreading layer (CSL). Accordingly, the constructed device achieves a (498 ± 11)% increase in $V_{SEB}$ while reducing the $R_{on,sp}$ by (41.8 ± 1.8)% compared with the traditional 4H-SiC LDMOS. This significantly enhances the device’s reliability in radiation environments.