Low-Power and Area-Efficient CIM: An SRAM-based fully-digital computing-in-memory hardware acceleration processor with approximate adder tree for multi-precision sparse neural networks

Abstract

Emergent architecture called computing-in-memory (CIM) effectively alleviates the issue of insufficient memory bandwidth and reduces energy consumption when accessing the on-chip buffer and registers. Some analog CIM macros designed to accelerate the neural network inference process have demonstrated significant improvements in both throughput and energy efficiency. These analog CIM macros are primarily utilized for neural networks with fixed activation and weight precision, which poses challenges for widespread deployment on edge devices with limited resources. On the other hand, analog macros exhibit heightened sensitivity to variations in process, voltage, and temperature, and the overhead associated with data conversion between analog and digital domains is unavoidable during calculation. Furthermore, exploring the sparse scheme compatible with CIM architecture can be beneficial in enhancing the energy efficiency of sparse neural network models. This article presents an SRAM-based fully-digital CIM hardware acceleration processor named Low-Power and Area-Efficient CIM (LPAE CIM), which combines the memory and computing macro of fully-digital architecture with peripheral storage and control modules to form a relatively comprehensive systematic structure. First, the sparsity of weight data is effectively utilized through a structured pruning method, and successive rows of the macro are opened flexibly for processing the sparsity of input activation. Second, the proposed area-friendly approximate adder tree replaces partial full adders with OR gates, reducing transistor count and promoting high-density integration of system-on-chip. Third, the shift adder outside the macro features dynamically adjustable 1–8 bit input activation and reconfigurable 4/8 bit storage weight, providing flexibility for fixed hardware resources. It achieves 148.5 TOPS/W energy efficiency at 4-bit activation and weight precision, which shows at least a 1.32× improvement over prior works.