Channel geometry-Driven performance enhancement under metal gate strain engineering in GAAFET

Metal Gate (MG) strain engineering has been employed in CMOS technology since the 45 nm node to enhance device performance. Since the MG strain engineering and corresponding performance enhancement critically depend on the geometry of the underlying channel, the dependency necessitates rigorous study of MG strain effects in advanced logic devices with diverse 3D channel architectures. In this work, we investigate the performance impact of MG-strained Si technology across FinFETs and nanosheet FETs (NSFETs) at the 3-nm node using 3D Technology Computer-Aided Design (TCAD) simulations. With the distinct channel geometry of NS, larger driving current enhancement (ΔI_on) and mobility enhancement (Δμ) are obtained on p-type NSFETs. Si channel strain distribution analysis shows that the performance enhancement can be attributed to the larger longitudinal (ZZ) compressive stress and the lateral (YY) tensile stress in the nanosheet channel. Subsequently, our investigation reveals that enhancing the effectiveness of MG strained Si technology in p-type NSFETs is achievable by reducing the nanosheet thickness or increasing its width.