基于0.18 μ V HV BCD工艺的1500 V/μs转换速率、300 MHz GBW运算放大器，用于CMOS系统级单片集成

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-10-06 DOI:10.1016/j.mejo.2025.106914

Jizhang Chen , Jueping Cai , Yuxin Zhang , Yixin Yin , Boming Tang

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引用次数: 0

摘要

为了实现CMOS系统级的单片集成，提出了一种基于BJT-CMOS混合结构的高压、高转速、大电流驱动、宽带运算放大器。与传统的互补双极（CB）工艺制造的高电压、高回转速率运放不同，该运放采用台积电0.18 μ v BCD工艺实现。BCD工艺中的bjt具有低电流增益（β），导致电流失配，电流驱动能力差，以及瞬态电流限制。为了减小电流失配引起的输入偏置电压，在ab类输入级引入互补偏置电流产生电路，保证PNP镜和NPN镜静态电流相等，在放大级引入基极电流采样反馈补偿电路，缓解电流失配。为了驱动大电流，使用cmos输出电流反馈缓冲器。为了避免信号转换过程中的电流限制和提高转换速率，采用了动态偏置架构。仿真结果表明，在±5 V电源下，该运算放大器的增益带宽积（GBW）为300 MHz，输入偏置电压为<；0.5 mV (3σ)，静态电流为6.2 mA。测量结果表明，在4 Vpp输出下，摆幅率超过1500 V/μs，运算放大器提供±50 mA（±100 mA）的负载电流，保持输出电压从−3.5 V到+ 3.4 V（从−3.2 V到+ 3.0 V）的摆动。

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A 1500 V/μs slew rate, 300 MHz GBW operational amplifier in 0.18-μm HV BCD process for CMOS system-level monolithic integration

A high-voltage, high-slew-rate, large-current-drive, wideband operational amplifier (op-amp) based on a hybrid BJT-CMOS architecture is proposed to enable CMOS system-level monolithic integration. Unlike conventional high-voltage, high-slew-rate op-amps fabricated in complementary bipolar (CB) process, the proposed op-amp is implemented in TSMC 0.18-

μ

m HV BCD process. BJTs in the BCD process exhibit low current gain (

β

), leading to current mismatch, poor current-driving capability, and limitations in transient current. In order to minimize the input offset voltage caused by current mismatch, a complementary bias current generation circuit is introduced in the class-AB input stage to guarantee equal static currents in PNP mirrors and NPN mirrors, and a base current-sampling feedback compensation circuit to mitigate current mismatch at the amplification stage. To drive large currents, the CMOS-output current-feedback buffer is used. To prevent current limitations and improve slew rate during signal conversion, a dynamic biasing architecture is adopted. Simulation results show that the op-amp achieves 300 MHz gain-bandwidth product (GBW) and

<

0.5 mV (3

σ

) input offset voltage consuming 6.2 mA quiescent current at ±5 V supply. Measurement results show that the slew rate exceeds 1500 V/

μ s

under 4

V_{pp}

output, and the op-amp delivers ±50 mA (±100 mA) of load current maintaining an output voltage swing from

-

3.5 V to ＋ 3.4 V (from

-

3.2 V to ＋ 3.0 V).

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.