Microelectronics Journal最新文献_第3页

A design of lightweight true random number generator based on Galois LFSR with dynamic feedback path

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-17 DOI: 10.1016/j.mejo.2025.106652

Zihao Miao , Huaguo Liang , Xin Li , Yingchun Lu , Liang Yao

{"title":"A design of lightweight true random number generator based on Galois LFSR with dynamic feedback path","authors":"Zihao Miao , Huaguo Liang , Xin Li , Yingchun Lu , Liang Yao","doi":"10.1016/j.mejo.2025.106652","DOIUrl":"10.1016/j.mejo.2025.106652","url":null,"abstract":"<div><div>The Linear Feedback Shift Register (LFSR) is a widely utilized circuit structure in electronic systems, often employed as a Pseudo Random Number Generator (PRNG) for generating pseudo random sequence. However, in light of the significant challenges associated with privacy protection and data encryption, traditional PRNGs have frequently failed to meet the increasing security demands of electronic systems. In contrast, True Random Number Generators (TRNGs), have emerged as essential security primitives within the realm of hardware security, garnering increasing attention. In response to these challenges, this paper proposes a novel lightweight TRNG architecture based on Galois LFSR. This innovation design incorporates inverters and two-to-one multiplexers to modify the feedback path. The proposed structure has been implemented on AMD Xilinx Artix-7 and Kintex-7 FPGA boards. Notably, it demonstrates a resource-efficient design, utilizing only 17 Look-Up Tables (LUTs) and 9 D Flip-Flops (DFFs), while achieving random number with throughput of 300Mbps. Furthermore, the structure successfully passes both randomness test and robustness test, indicating its promising application potential in secure electronic systems.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106652"},"PeriodicalIF":1.9,"publicationDate":"2025-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143644528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A residual pulse broadening interpolation quantization column-level ADC architecture for CMOS image sensors

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-15 DOI: 10.1016/j.mejo.2025.106638

Qiang Zhao , Ziming Wang , Chunhui Fan , Bin Qiang , Jitao Xu , Xin Li , Zhigang Li , Licai Hao , Chunyu Peng , Zhiting Lin , Xiulong Wu

引用次数: 0

Enhanced platform-based interrupt controller for RISC-V MCUs

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-13 DOI: 10.1016/j.mejo.2025.106628

Yang Ren , Nianxiong Tan

{"title":"Enhanced platform-based interrupt controller for RISC-V MCUs","authors":"Yang Ren , Nianxiong Tan","doi":"10.1016/j.mejo.2025.106628","DOIUrl":"10.1016/j.mejo.2025.106628","url":null,"abstract":"<div><div>Interrupt efficiency including latency is a critical factor in the performance of real-time embedded microcontroller units (MCUs) used for the internet of things (IoT). RISC-V MCUs often suffer from greater interrupt latency due to the extensive software intervention required by the conventional Platform-Level Interrupt Controller (PLIC), in contrast to ARM Cortex-M MCUs that employ hardware-accelerated, vectored interrupt handling. Although the Core Local Interrupt Controller (CLIC) has mitigated some latency issues, its lack of native support in many open-source RISC-V cores restricts its widespread adoption. This work introduces an Enhanced PLIC (EPLIC) that incorporates hardware-accelerated features such as vectored scheduling, context saving and restoration, interrupt nesting, and tail-chaining to optimize the Interrupt Service Routine (ISR). Implemented in the open-source Ibex core, EPLIC not only substantially reduces interrupt latency to 7 clock cycles but also achieves interrupt performance on par with commercial MCUs based on ARM’s Cortex-M processors. This work had been implemented in a smart electricity meter System-on-Chip (SoC).</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106628"},"PeriodicalIF":1.9,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143641726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel NMOSFET-embedded high holding voltage SCR for 5-V applications

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-13 DOI: 10.1016/j.mejo.2025.106625

Hongshen Wang , Lingli Qian , Zhiyu Wang , Yuanjie Zhou , Qian Liu , Hao Wu , Jian Shen , Juan Luo , Shengdong Hu

{"title":"A novel NMOSFET-embedded high holding voltage SCR for 5-V applications","authors":"Hongshen Wang , Lingli Qian , Zhiyu Wang , Yuanjie Zhou , Qian Liu , Hao Wu , Jian Shen , Juan Luo , Shengdong Hu","doi":"10.1016/j.mejo.2025.106625","DOIUrl":"10.1016/j.mejo.2025.106625","url":null,"abstract":"<div><div>This study presents a novel NMOSFET-embedded high holding voltage silicon-controlled rectifier (NNEHHVSCR). In this structure, based on the conventional low-trigger SCR with added P+ bridge regions, the NMOSFET is further embedded, supplemented with external electrical connections. This configuration creates multiple ESD current paths to divert current, thereby enhancing the holding voltage. The working principle and <em>I</em>-<em>V</em> characteristic curves of the proposed structure are simulated using Sentaurus TCAD software. The results show that, compared to the reference device, while maintaining a nearly unchanged trigger voltage (<em>V</em><sub>t1</sub>), the NNEHHVSCR significantly increases the holding voltage (<em>V</em><sub>h</sub>) from 3.89 V to 6.03 V, surpassing the lower voltage limit defined by the 5-V ESD design window. Meanwhile, the failure current (<em>I</em><sub>t2</sub>) only decreases slightly from 2.00 A to 1.89 A, with an acceptable trade-off. Therefore, the NNEHHVSCR demonstrates excellent latch-up immunity and ESD robustness, making it suitable for 5-V ESD applications.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106625"},"PeriodicalIF":1.9,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143644527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A two-phase oscillation scheme with direct background correction for VCO-based ADC

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-13 DOI: 10.1016/j.mejo.2025.106644

Tao Zhong , Yuekang Guo , Jing Jin , Jianjun Zhou

引用次数: 0

A programmable high efficiency charge pump system for embedded flash memory with improved current driving capability

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-12 DOI: 10.1016/j.mejo.2025.106626

Tao Xu, Yuqiao Xie, Guoji Qiu, Zhiyuan Hu, Zhengxuan Zhang, Dawei Bi

{"title":"A programmable high efficiency charge pump system for embedded flash memory with improved current driving capability","authors":"Tao Xu, Yuqiao Xie, Guoji Qiu, Zhiyuan Hu, Zhengxuan Zhang, Dawei Bi","doi":"10.1016/j.mejo.2025.106626","DOIUrl":"10.1016/j.mejo.2025.106626","url":null,"abstract":"<div><div>Flash memory, a key element in embedded systems, necessitates high voltage for its operation, which is usually provided by charge pumps. This paper presents a programmable high efficiency charge pump system in 40 nm bulk CMOS technology powered from a 1.1 V supply. The proposed system integrates low-voltage MOS self-adaptive body-biased cross-coupled charge pumps and a high-voltage MOS self-adaptive body-biased cross-coupled charge pump with a doubler structure. The system adaptively activates the appropriate charge pump combination based on the current load, working in conjunction with a novel clock coupled voltage modulation circuit to achieve reduced power consumption and improved efficiency. The programmable high efficiency charge pump system can stabilize an output voltage of 6V at <span><math><mrow><mn>292</mn><mspace></mspace><mi>μ</mi><mi>A</mi></mrow></math></span> and 8V at <span><math><mrow><mn>235</mn><mspace></mspace><mi>μ</mi><mi>A</mi></mrow></math></span> under a 50 MHz clock. It achieves a peak efficiency of 64.04% at <span><math><mrow><mn>292</mn><mspace></mspace><mi>μ</mi><mi>A</mi></mrow></math></span> current load and occupies 0.145 mm<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span> in area.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106626"},"PeriodicalIF":1.9,"publicationDate":"2025-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143619233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis of superjunction structure of fast switching loss IGBT with non-equivalent segmented anode NPN

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-11 DOI: 10.1016/j.mejo.2025.106642

Zhiyong Qiu, Quanyuan Feng, Bokang Huang, Qiqi Liu

{"title":"Analysis of superjunction structure of fast switching loss IGBT with non-equivalent segmented anode NPN","authors":"Zhiyong Qiu, Quanyuan Feng, Bokang Huang, Qiqi Liu","doi":"10.1016/j.mejo.2025.106642","DOIUrl":"10.1016/j.mejo.2025.106642","url":null,"abstract":"<div><div>To reduce switching losses and improve the breakdown voltage of IGBTs, a novel superjunction IGBT structure with a non-equivalent segmented anode NPN transistor (NSA-SJ-IGBT) is proposed, along with a simulation study of its performance. The proposed structure incorporates a collector region embedded with a non-equivalent segmented anode NPN transistor. By optimizing the concentration and thickness of the P-type region in the NPN transistor of the NSA-SJ-IGBT, electron extraction during the turn-off process is accelerated, resulting in a significant reduction in turn-off losses. Additionally, during the turn-on process, the NSA-SJ-IGBT benefits from a more direct flow path for both electrons and holes, as well as a more uniform distribution of electron and hole densities, which facilitates faster and more efficient turn-on. Compared to the NSA-BJSJ-IGBT structure, the NSA-SJ-IGBT exhibits a reduction of approximately 38.7 % in turn-on losses at the same forward conduction voltage, while maintaining similar breakdown voltage and turn-off losses. When compared to the BJSJ-IGBT, under equivalent conditions and comparable forward conduction voltage, the NSA-SJ-IGBT demonstrates a 41 % reduction in turn-off losses, a 32 % reduction in turn-on losses, and an improvement in breakdown voltage. Furthermore, the NSA-SJ-IGBT offers significant design flexibility, enabling better optimization of the trade-off between turn-off loss and conduction voltage drop by adjusting the embedded NPN transistor, thereby enhancing overall device performance.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106642"},"PeriodicalIF":1.9,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143686091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Taylor modeling and comparative research containing aspect-ratio dependent optimization of three-dimensional Hk superjunction MOSFETs

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-11 DOI: 10.1016/j.mejo.2025.106623

Haimeng Huang, Zhentao Xiao, Zonghao Zhang, Chenxing Wang, Hongqiang Yang

{"title":"Taylor modeling and comparative research containing aspect-ratio dependent optimization of three-dimensional Hk superjunction MOSFETs","authors":"Haimeng Huang, Zhentao Xiao, Zonghao Zhang, Chenxing Wang, Hongqiang Yang","doi":"10.1016/j.mejo.2025.106623","DOIUrl":"10.1016/j.mejo.2025.106623","url":null,"abstract":"<div><div>A proposed optimization for high-<em>k</em> superjunction (H<span><math><mi>k</mi></math></span>-SJ) MOSFETs focuses on reducing specific ON-resistance (<em>R</em><span><math><msub><mrow></mrow><mrow><mi>on,sp</mi></mrow></msub></math></span>) in drift regions for three dimensional (3D) configurations in two cases (3DH<span><math><mi>k</mi></math></span>core and 3DH<span><math><mi>k</mi></math></span>shell) compared to 3D conventional SJ (C-SJ) and two dimensional Hk-SJ (2DH<span><math><mi>k</mi></math></span>). Under constraints of avalanche breakdown and critical depletion, the optimized <em>R</em><span><math><msub><mrow></mrow><mrow><mi>on,sp</mi></mrow></msub></math></span> and design parameters are determined. 3DH<span><math><mi>k</mi></math></span>core achieves the lowest <em>R</em><span><math><msub><mrow></mrow><mrow><mi>on,sp</mi></mrow></msub></math></span> of 12.43 m<span><math><mrow><mi>Ω</mi><mspace></mspace><msup><mrow><mi>cm</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span> at 800 V breakdown voltage (BV) for small aspect ratios (AR) due to the lower breakdown electric field (<span><math><mi>E</mi></math></span>-field) and impact ionization integral value, while 3DH<span><math><mi>k</mi></math></span>shell excels 3DH<span><math><mi>k</mi></math></span>core and 2DH<span><math><mi>k</mi></math></span> with a lower <em>R</em><span><math><msub><mrow></mrow><mrow><mi>on,sp</mi></mrow></msub></math></span> of 6.395 m<span><math><mrow><mi>Ω</mi><mspace></mspace><msup><mrow><mi>cm</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span> at large AR. Comparative research containing charge imbalance, temperature robustness, and switching characteristics is discussed after optimization. Taylor modeling for 3DH<span><math><mi>k</mi></math></span>shell optimization is also proposed. For further manufacturing guidance, fitting and boundary curves formulas are provided.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106623"},"PeriodicalIF":1.9,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143610335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of wide stopband high-selectivity filter based on ICL-CS

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-10 DOI: 10.1016/j.mejo.2025.106624

Zikai Wu , Guiqiang Guo , Guodong Su , Bin You , Yongmei Pan , Jun Liu

引用次数: 0

A deep trench-type SiC MOSFET integrated with Schottky diode for enhanced oxide reliability and switching performances

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-07 DOI: 10.1016/j.mejo.2025.106639

Liang Tian, Qingchun Zhang

{"title":"A deep trench-type SiC MOSFET integrated with Schottky diode for enhanced oxide reliability and switching performances","authors":"Liang Tian, Qingchun Zhang","doi":"10.1016/j.mejo.2025.106639","DOIUrl":"10.1016/j.mejo.2025.106639","url":null,"abstract":"<div><div>This paper presents a novel deep trench-type SiC MOSFET integrated with Schottky diodes (DT-JMOS) designed to improve oxide reliability and switching performances. In contrast to conventional SiC trench MOSFET with Schottky diodes (CT-JMOS), the DT-JMOS utilizes a narrower JFET region and a P-bot structure, resulting in superior electric field reductions in gate oxide layer to improve reliability. The unique structure also enables double-channel operation and deeper embedded Schottky contacts, significantly enhancing the current conduction capabilities in both the first and third quadrants. Furthermore, simulation results indicate that the DT-JMOS achieves a 97.6 % decrease in gate-to-drain capacitance (<em>C</em><sub>gd</sub>), leading to a 67.5 % improvement in gate-to-drain charge (<em>Q</em><sub>gd</sub>), and eventually resulting in reductions by factors of 3.2 and 3.5 for figure of merit <em>Q</em><sub>gd</sub> × <em>R</em><sub>on,sp</sub> and total switching losses (<em>E</em><sub>total</sub>), respectively. These attributes suggest that the DT-JMOS is more suitable for high-voltage and high-frequency applications.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106639"},"PeriodicalIF":1.9,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143577946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0