Microelectronics Journal最新文献

筛选
英文 中文
A novel NMOSFET-embedded high holding voltage SCR for 5-V applications
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-03-13 DOI: 10.1016/j.mejo.2025.106625
Hongshen Wang , Lingli Qian , Zhiyu Wang , Yuanjie Zhou , Qian Liu , Hao Wu , Jian Shen , Juan Luo , Shengdong Hu
{"title":"A novel NMOSFET-embedded high holding voltage SCR for 5-V applications","authors":"Hongshen Wang ,&nbsp;Lingli Qian ,&nbsp;Zhiyu Wang ,&nbsp;Yuanjie Zhou ,&nbsp;Qian Liu ,&nbsp;Hao Wu ,&nbsp;Jian Shen ,&nbsp;Juan Luo ,&nbsp;Shengdong Hu","doi":"10.1016/j.mejo.2025.106625","DOIUrl":"10.1016/j.mejo.2025.106625","url":null,"abstract":"<div><div>This study presents a novel NMOSFET-embedded high holding voltage silicon-controlled rectifier (NNEHHVSCR). In this structure, based on the conventional low-trigger SCR with added P+ bridge regions, the NMOSFET is further embedded, supplemented with external electrical connections. This configuration creates multiple ESD current paths to divert current, thereby enhancing the holding voltage. The working principle and <em>I</em>-<em>V</em> characteristic curves of the proposed structure are simulated using Sentaurus TCAD software. The results show that, compared to the reference device, while maintaining a nearly unchanged trigger voltage (<em>V</em><sub>t1</sub>), the NNEHHVSCR significantly increases the holding voltage (<em>V</em><sub>h</sub>) from 3.89 V to 6.03 V, surpassing the lower voltage limit defined by the 5-V ESD design window. Meanwhile, the failure current (<em>I</em><sub>t2</sub>) only decreases slightly from 2.00 A to 1.89 A, with an acceptable trade-off. Therefore, the NNEHHVSCR demonstrates excellent latch-up immunity and ESD robustness, making it suitable for 5-V ESD applications.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106625"},"PeriodicalIF":1.9,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143644527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A two-phase oscillation scheme with direct background correction for VCO-based ADC
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-03-13 DOI: 10.1016/j.mejo.2025.106644
Tao Zhong , Yuekang Guo , Jing Jin , Jianjun Zhou
{"title":"A two-phase oscillation scheme with direct background correction for VCO-based ADC","authors":"Tao Zhong ,&nbsp;Yuekang Guo ,&nbsp;Jing Jin ,&nbsp;Jianjun Zhou","doi":"10.1016/j.mejo.2025.106644","DOIUrl":"10.1016/j.mejo.2025.106644","url":null,"abstract":"<div><div>This paper presents a two-phase oscillation scheme for ring voltage-controlled oscillator (VCO) based ADC to directly correct the deviation of the actual V-to-F transfer characteristic, including nonlinearity and the deviation of the tuning gain and center frequency. The proposed scheme facilitates correction of these non-idealities by injecting opposing signals during two phases while preserving output phase continuity, operating in the background without the need for replicas, dithering, or stringent input restrictions. Designed and simulated in 40 nm CMOS process, the variation of the tuning gain and center frequency of the ring VCO across different process, voltage, temperature (PVT) corners are within ±17 % and ±16 %, respectively, which results in gain error and offset problems in the ADC. By applying the proposed correction techniques, both these two errors can be corrected within ±1 %. Moreover, the maximum distortion can be reduced by 35.06 dB, and the signal-to-noise-and-distortion ratio (SNDR) can be improved from 50.39 dB to 75.37 dB.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106644"},"PeriodicalIF":1.9,"publicationDate":"2025-03-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143685619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A programmable high efficiency charge pump system for embedded flash memory with improved current driving capability
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-03-12 DOI: 10.1016/j.mejo.2025.106626
Tao Xu, Yuqiao Xie, Guoji Qiu, Zhiyuan Hu, Zhengxuan Zhang, Dawei Bi
{"title":"A programmable high efficiency charge pump system for embedded flash memory with improved current driving capability","authors":"Tao Xu,&nbsp;Yuqiao Xie,&nbsp;Guoji Qiu,&nbsp;Zhiyuan Hu,&nbsp;Zhengxuan Zhang,&nbsp;Dawei Bi","doi":"10.1016/j.mejo.2025.106626","DOIUrl":"10.1016/j.mejo.2025.106626","url":null,"abstract":"<div><div>Flash memory, a key element in embedded systems, necessitates high voltage for its operation, which is usually provided by charge pumps. This paper presents a programmable high efficiency charge pump system in 40 nm bulk CMOS technology powered from a 1.1 V supply. The proposed system integrates low-voltage MOS self-adaptive body-biased cross-coupled charge pumps and a high-voltage MOS self-adaptive body-biased cross-coupled charge pump with a doubler structure. The system adaptively activates the appropriate charge pump combination based on the current load, working in conjunction with a novel clock coupled voltage modulation circuit to achieve reduced power consumption and improved efficiency. The programmable high efficiency charge pump system can stabilize an output voltage of 6V at <span><math><mrow><mn>292</mn><mspace></mspace><mi>μ</mi><mi>A</mi></mrow></math></span> and 8V at <span><math><mrow><mn>235</mn><mspace></mspace><mi>μ</mi><mi>A</mi></mrow></math></span> under a 50 MHz clock. It achieves a peak efficiency of 64.04% at <span><math><mrow><mn>292</mn><mspace></mspace><mi>μ</mi><mi>A</mi></mrow></math></span> current load and occupies 0.145 mm<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span> in area.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106626"},"PeriodicalIF":1.9,"publicationDate":"2025-03-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143619233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of superjunction structure of fast switching loss IGBT with non-equivalent segmented anode NPN
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-03-11 DOI: 10.1016/j.mejo.2025.106642
Zhiyong Qiu, Quanyuan Feng, Bokang Huang, Qiqi Liu
{"title":"Analysis of superjunction structure of fast switching loss IGBT with non-equivalent segmented anode NPN","authors":"Zhiyong Qiu,&nbsp;Quanyuan Feng,&nbsp;Bokang Huang,&nbsp;Qiqi Liu","doi":"10.1016/j.mejo.2025.106642","DOIUrl":"10.1016/j.mejo.2025.106642","url":null,"abstract":"<div><div>To reduce switching losses and improve the breakdown voltage of IGBTs, a novel superjunction IGBT structure with a non-equivalent segmented anode NPN transistor (NSA-SJ-IGBT) is proposed, along with a simulation study of its performance. The proposed structure incorporates a collector region embedded with a non-equivalent segmented anode NPN transistor. By optimizing the concentration and thickness of the P-type region in the NPN transistor of the NSA-SJ-IGBT, electron extraction during the turn-off process is accelerated, resulting in a significant reduction in turn-off losses. Additionally, during the turn-on process, the NSA-SJ-IGBT benefits from a more direct flow path for both electrons and holes, as well as a more uniform distribution of electron and hole densities, which facilitates faster and more efficient turn-on. Compared to the NSA-BJSJ-IGBT structure, the NSA-SJ-IGBT exhibits a reduction of approximately 38.7 % in turn-on losses at the same forward conduction voltage, while maintaining similar breakdown voltage and turn-off losses. When compared to the BJSJ-IGBT, under equivalent conditions and comparable forward conduction voltage, the NSA-SJ-IGBT demonstrates a 41 % reduction in turn-off losses, a 32 % reduction in turn-on losses, and an improvement in breakdown voltage. Furthermore, the NSA-SJ-IGBT offers significant design flexibility, enabling better optimization of the trade-off between turn-off loss and conduction voltage drop by adjusting the embedded NPN transistor, thereby enhancing overall device performance.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106642"},"PeriodicalIF":1.9,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143686091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Taylor modeling and comparative research containing aspect-ratio dependent optimization of three-dimensional Hk superjunction MOSFETs
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-03-11 DOI: 10.1016/j.mejo.2025.106623
Haimeng Huang, Zhentao Xiao, Zonghao Zhang, Chenxing Wang, Hongqiang Yang
{"title":"Taylor modeling and comparative research containing aspect-ratio dependent optimization of three-dimensional Hk superjunction MOSFETs","authors":"Haimeng Huang,&nbsp;Zhentao Xiao,&nbsp;Zonghao Zhang,&nbsp;Chenxing Wang,&nbsp;Hongqiang Yang","doi":"10.1016/j.mejo.2025.106623","DOIUrl":"10.1016/j.mejo.2025.106623","url":null,"abstract":"<div><div>A proposed optimization for high-<em>k</em> superjunction (H<span><math><mi>k</mi></math></span>-SJ) MOSFETs focuses on reducing specific ON-resistance (<em>R</em><span><math><msub><mrow></mrow><mrow><mi>on,sp</mi></mrow></msub></math></span>) in drift regions for three dimensional (3D) configurations in two cases (3DH<span><math><mi>k</mi></math></span>core and 3DH<span><math><mi>k</mi></math></span>shell) compared to 3D conventional SJ (C-SJ) and two dimensional Hk-SJ (2DH<span><math><mi>k</mi></math></span>). Under constraints of avalanche breakdown and critical depletion, the optimized <em>R</em><span><math><msub><mrow></mrow><mrow><mi>on,sp</mi></mrow></msub></math></span> and design parameters are determined. 3DH<span><math><mi>k</mi></math></span>core achieves the lowest <em>R</em><span><math><msub><mrow></mrow><mrow><mi>on,sp</mi></mrow></msub></math></span> of 12.43 m<span><math><mrow><mi>Ω</mi><mspace></mspace><msup><mrow><mi>cm</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span> at 800 V breakdown voltage (BV) for small aspect ratios (AR) due to the lower breakdown electric field (<span><math><mi>E</mi></math></span>-field) and impact ionization integral value, while 3DH<span><math><mi>k</mi></math></span>shell excels 3DH<span><math><mi>k</mi></math></span>core and 2DH<span><math><mi>k</mi></math></span> with a lower <em>R</em><span><math><msub><mrow></mrow><mrow><mi>on,sp</mi></mrow></msub></math></span> of 6.395 m<span><math><mrow><mi>Ω</mi><mspace></mspace><msup><mrow><mi>cm</mi></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span> at large AR. Comparative research containing charge imbalance, temperature robustness, and switching characteristics is discussed after optimization. Taylor modeling for 3DH<span><math><mi>k</mi></math></span>shell optimization is also proposed. For further manufacturing guidance, fitting and boundary curves formulas are provided.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106623"},"PeriodicalIF":1.9,"publicationDate":"2025-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143610335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of wide stopband high-selectivity filter based on ICL-CS
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-03-10 DOI: 10.1016/j.mejo.2025.106624
Zikai Wu , Guiqiang Guo , Guodong Su , Bin You , Yongmei Pan , Jun Liu
{"title":"Design of wide stopband high-selectivity filter based on ICL-CS","authors":"Zikai Wu ,&nbsp;Guiqiang Guo ,&nbsp;Guodong Su ,&nbsp;Bin You ,&nbsp;Yongmei Pan ,&nbsp;Jun Liu","doi":"10.1016/j.mejo.2025.106624","DOIUrl":"10.1016/j.mejo.2025.106624","url":null,"abstract":"<div><div>This paper presents an inter-digital coupled line structure loaded with composite stubs (ICL-CS) to achieve high selectivity and a broad frequency range. The design uses triple-line coupling to minimize in-band insertion loss and composite stubs to expand the passband and stopband of the bandpass filter (BPF). Compared to traditional triple-line coupling structures, the ICL-CS offers a significantly wider stopband. The cascade response of triple-line coupling and composite branch nodes is analyzed using an extended odd-even mode method, systematically evaluating the frequency response. Based on this structure, a high-performance BPF is proposed with a wide stopband and excellent selectivity. Experimental results show an operating frequency range of 8.3 GHz to 15.2 GHz, an insertion loss of 2.6 dB, a shape factor of 1.22, and an out-of-band rejection of 26 dB across the stopband range of 16.4 GHz to 34 GHz. This filter is highly suitable for three-dimensional heterogeneous wireless communication systems.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106624"},"PeriodicalIF":1.9,"publicationDate":"2025-03-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143619232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A deep trench-type SiC MOSFET integrated with Schottky diode for enhanced oxide reliability and switching performances
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-03-07 DOI: 10.1016/j.mejo.2025.106639
Liang Tian, Qingchun Zhang
{"title":"A deep trench-type SiC MOSFET integrated with Schottky diode for enhanced oxide reliability and switching performances","authors":"Liang Tian,&nbsp;Qingchun Zhang","doi":"10.1016/j.mejo.2025.106639","DOIUrl":"10.1016/j.mejo.2025.106639","url":null,"abstract":"<div><div>This paper presents a novel deep trench-type SiC MOSFET integrated with Schottky diodes (DT-JMOS) designed to improve oxide reliability and switching performances. In contrast to conventional SiC trench MOSFET with Schottky diodes (CT-JMOS), the DT-JMOS utilizes a narrower JFET region and a P-bot structure, resulting in superior electric field reductions in gate oxide layer to improve reliability. The unique structure also enables double-channel operation and deeper embedded Schottky contacts, significantly enhancing the current conduction capabilities in both the first and third quadrants. Furthermore, simulation results indicate that the DT-JMOS achieves a 97.6 % decrease in gate-to-drain capacitance (<em>C</em><sub>gd</sub>), leading to a 67.5 % improvement in gate-to-drain charge (<em>Q</em><sub>gd</sub>), and eventually resulting in reductions by factors of 3.2 and 3.5 for figure of merit <em>Q</em><sub>gd</sub> × <em>R</em><sub>on,sp</sub> and total switching losses (<em>E</em><sub>total</sub>), respectively. These attributes suggest that the DT-JMOS is more suitable for high-voltage and high-frequency applications.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106639"},"PeriodicalIF":1.9,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143577946","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 28 nm Ising machine with adaptive majority voter and reduction algorithms for high-performance combinatorial optimization
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-03-07 DOI: 10.1016/j.mejo.2025.106621
Jingyang Chen , Zhiping Yu , Xiaolei Zhu
{"title":"A 28 nm Ising machine with adaptive majority voter and reduction algorithms for high-performance combinatorial optimization","authors":"Jingyang Chen ,&nbsp;Zhiping Yu ,&nbsp;Xiaolei Zhu","doi":"10.1016/j.mejo.2025.106621","DOIUrl":"10.1016/j.mejo.2025.106621","url":null,"abstract":"<div><div>The Ising model has shown outstanding potential for solving combinatorial optimization problems, but conventional processors based on the von Neumann architecture have difficulty emulating the behavior of spins in parallel. Therefore, to tackle combinatorial optimization problems efficiently, specialized processors with Ising models are required. In this work, an approximate logistic complementary spin update (ALCU) model is proposed that enhances the accuracy of the solution by 3.34% compared to the previous approximation methodology. In addition, an adaptive analog majority voter (AMV) is proposed, which can support higher interaction coefficient bit-width and more interaction spins with lower hardware overhead. Then, the Ising machine with 100 interaction spins in King’s Graph topology is implemented based on a 28 nm CMOS process. More than 67% less hardware overhead is required when compared to Ising machines based on digital adders. The coefficient precision is increased to 2.3x, and the number of interaction spins is increased to 1.6x compared to the Ising machine based on prior AMV.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106621"},"PeriodicalIF":1.9,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143619231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A VRO-based TDC with a constant timing resolution ratio between coarse-tuning and fine-tuning stages for a light sensor application
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-03-07 DOI: 10.1016/j.mejo.2025.106637
Jen-Chieh Liu , Jian-Sheng Li , Yan-Xun Chen , Yu-Lung Lo
{"title":"A VRO-based TDC with a constant timing resolution ratio between coarse-tuning and fine-tuning stages for a light sensor application","authors":"Jen-Chieh Liu ,&nbsp;Jian-Sheng Li ,&nbsp;Yan-Xun Chen ,&nbsp;Yu-Lung Lo","doi":"10.1016/j.mejo.2025.106637","DOIUrl":"10.1016/j.mejo.2025.106637","url":null,"abstract":"<div><div>This study designs a vernier ring oscillator (VRO)-based time-to-digital converter (TDC), ensuring a proportional relationship between the timing resolutions of the coarse-tuning stage (CTS) and fine-tuning stage (FTS) under process, voltage, and temperature (PVT) variations. The design allows flexibility in extending the bit number to a wide input range during CTS. The timing resolutions of CTS and FTS were defined by the rise and fall times. Therefore, the timing ratio between CTS and FTS of VRO-based TDC remained constant under the PVT variations. This 14-bit TDC was fabricated using a 0.18 μm standard CMOS process with a core area of 45 μm × 200 μm. The measured timing resolution of the proposed VRO-based TDC was 125 ps, and the input range was from 10 to 200 ns. The DNL and INL values were less than ±0.244 and ± 0.336 LSB, respectively. The proposed VRO-based TDC was also integrated with a light sensor for Internet of Things applications.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106637"},"PeriodicalIF":1.9,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143592900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Enhanced performance of p-GaN HEMT via partial etched AlGaN
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2025-03-05 DOI: 10.1016/j.mejo.2025.106627
Qingxin Liu , Shuang Wu , Kailin Ren , Luqiao Yin , Jianhua Zhang
{"title":"Enhanced performance of p-GaN HEMT via partial etched AlGaN","authors":"Qingxin Liu ,&nbsp;Shuang Wu ,&nbsp;Kailin Ren ,&nbsp;Luqiao Yin ,&nbsp;Jianhua Zhang","doi":"10.1016/j.mejo.2025.106627","DOIUrl":"10.1016/j.mejo.2025.106627","url":null,"abstract":"<div><div>P-GaN high electron mobility transistor (HEMT) is currently the most commonly used enhanced GaN HEMT device. However, due to the presence of defects and traps, as well as the strong self-heating effect, p-GaN HEMT faces challenges with low breakdown voltage and poor device stability. In this study, a p-GaN HEMT structure via partially etched AlGaN has been proposed. The electrical and thermal performances of this device are thoroughly characterized and compared with conventional p-GaN HEMT. Through the proposed device structure, the breakdown voltage is increased from 290 V to 480 V, representing a 65 % improvement compared to conventional HEMT fabricated on the same wafer. The self-heating effect is also suppressed, resulting in a temperature reduction of 41.76 °C at a power level of 3.48 W. And more distinct temperature contrast images are obtained through thermoreflectance thermal imaging technology. This study provides a potential solution for fully leveraging the performance of p-GaN HEMT devices.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106627"},"PeriodicalIF":1.9,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143577538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信