Microelectronics Journal最新文献_第3页

A low-power 18-bit sigma-delta digital-to-analog converter with low-temperature-drift reference 具有低温漂移基准的低功耗18位σ - δ数模转换器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-30 DOI: 10.1016/j.mejo.2025.106716

Xingyuan Tong , Hao Yu , Xin Xin , Yuhua Liang

{"title":"A low-power 18-bit sigma-delta digital-to-analog converter with low-temperature-drift reference","authors":"Xingyuan Tong , Hao Yu , Xin Xin , Yuhua Liang","doi":"10.1016/j.mejo.2025.106716","DOIUrl":"10.1016/j.mejo.2025.106716","url":null,"abstract":"<div><div>An 18-bit Σ-Δ digital-to-analog converter (DAC) with precision-trimmed bandgap reference is proposed for industrial transmitters. A bandgap reference with an 8-bit trimming DAC and a high-order compensation circuit for reducing the temperature coefficient (TC) affected by process and voltage variation was utilized, which effectively guarantees the robustness of the Σ-Δ DAC. Compared with the conventional Σ-Δ DAC, the proposed DAC replaces the on-chip digital interpolation filter (IF) by providing oversampled input digital codes, and a low-pass configurable off-chip passive RC filter is utilized for power reduction. A quantization noise randomization scheme was employed by adding pseudo-random sequences in the Σ-Δ modulator, achieving 27.22 dB improvement in signal-to-noise and distortion ratio (SNDR) with 0.045 mW increase in power consumption. The proposed Σ-Δ DAC is designed with 180 nm CMOS technology with a supply voltage of 3.3 V. Benefiting from the optimization of the filtering mode and the precision trimming technique of the bandgap reference, an SNDR of 108.01 dB was achieved with a power consumption of 0.257 mW. In the temperature range of -40–105 °C, the temperature coefficient of the DAC output was less than 25.83 ppm/°C, under different process conditions.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"161 ","pages":"Article 106716"},"PeriodicalIF":1.9,"publicationDate":"2025-04-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143894515","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Proposal of a multi-bit cell scheme for spin-orbit torque MRAM array to implement 16 Boolean logic operations 提出了一种实现16个布尔逻辑运算的自旋轨道转矩MRAM阵列多比特单元方案

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-28 DOI: 10.1016/j.mejo.2025.106711

Jie Liu , Pingfan Ning , Delin Zhang , Pingjuan Niu , Yong Jiang

{"title":"Proposal of a multi-bit cell scheme for spin-orbit torque MRAM array to implement 16 Boolean logic operations","authors":"Jie Liu , Pingfan Ning , Delin Zhang , Pingjuan Niu , Yong Jiang","doi":"10.1016/j.mejo.2025.106711","DOIUrl":"10.1016/j.mejo.2025.106711","url":null,"abstract":"<div><div>Magnetic random access memory (MRAM) is a promising applicant for universal memory in the post-Moore age, due to its beneficial characteristics in terms of energy efficiency, integration, and endurance. Spin-orbit torque (SOT) MRAM for logic-in-memory (LIM) is a highly anticipated method for processing-in-memory (PIM) to address the von Neumann bottleneck. We present a flexible SOT-MRAM array cell scheme capable of storing multiple bits and executing 16 complete Boolean logic operations. Two magnetic tunnel junctions (MTJs) utilizing SOT and voltage-controlled magnetic anisotropy (VCMA) effects, combined with three transistors, form a 3T2M cell capable of four resistance states (2-bit) for data storage, necessitating a minimum average power consumption of 2.483 fJ/bit for writing. The two operational steps of all-electrical modulation, comprising the write and logic operations, are adequate to execute the 16 Boolean logics in situ. These findings may provide a basis for the development of adaptable and programmable LIM techniques for reconfigurable digital PIM architectures.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"161 ","pages":"Article 106711"},"PeriodicalIF":1.9,"publicationDate":"2025-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143891633","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A new quasi-3D analytical framework for channel potential and threshold voltage in triple material gate nanosheet MOSFETs 三材料栅极纳米片mosfet通道电位和阈值电压的准三维分析框架

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-28 DOI: 10.1016/j.mejo.2025.106710

E. Rajalakshmi , N.B. Balamurugan , M. Suguna , D. Sriram Kumar

{"title":"A new quasi-3D analytical framework for channel potential and threshold voltage in triple material gate nanosheet MOSFETs","authors":"E. Rajalakshmi , N.B. Balamurugan , M. Suguna , D. Sriram Kumar","doi":"10.1016/j.mejo.2025.106710","DOIUrl":"10.1016/j.mejo.2025.106710","url":null,"abstract":"<div><div>Nanosheet MOSFETs is an excellent replacement for FinFETs for sub-5 nm technology nodes because of their outstanding electrostatic control provided by their gate-all-around structure. A novel Triple Material Gate nanosheet MOSFETs is presented in this work. For the first time, an analytical model for the threshold voltage and channel potential is derived using a quasi-3D approach. Through consideration of both vertical and a lateral potential fluctuation, the proposed model effectively depicts electrostatic behavior. Ballistic transport theory is utilized to assess subthreshold swing and threshold voltage characteristics, improving the accuracy of predictions. The results demonstrate an 11.3 % drop in subthreshold swing and a 10 % reduction in threshold voltage, assuring improved device performance. The proposed TMG-NS-MOSFETs achieve a high current ON and OFF ratio of 2.4 × 10<sup>6</sup> at 20 nm gate length, ensuring excellent switching performance. A significant correlation is confirmed via validation against TCAD simulations, proving the model's dependability. This novel analytical approach advances the modeling of semiconductor devices by offering better insights into nanosheet MOSFETs electrostatics. Based on the results, new nanosheet MOSFETs designs can be incorporated into ultra-low power, high performance microelectronic circuits of the future.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"161 ","pages":"Article 106710"},"PeriodicalIF":1.9,"publicationDate":"2025-04-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143887647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A PVT-insensitive 7T SRAM CIM macro for multibit multiplication with dynamic matching quantization circuits 一个pvt不敏感的7T SRAM CIM宏，用于动态匹配量化电路的多位乘法

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-26 DOI: 10.1016/j.mejo.2025.106703

Chenghu Dai , Jianhao Zhang , Ruixuan Wang , Junbo Chen , Wei Hu , Licai Hao , Wenjuan Lu , Zhiting Lin , Chunyu Peng , Xiulong Wu

引用次数: 0

A RISC-V based SoC for blockchain data integration in IoT edge devices 基于RISC-V的SoC，用于物联网边缘设备中的区块链数据集成

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-24 DOI: 10.1016/j.mejo.2025.106697

Wentao Xu , Xiang Li , Qiuyan Xu , Yuxuan Zhang , Xiang Wu , Weilin Li , Ruize Wang , Gang Liang , Hao Guo

{"title":"A RISC-V based SoC for blockchain data integration in IoT edge devices","authors":"Wentao Xu , Xiang Li , Qiuyan Xu , Yuxuan Zhang , Xiang Wu , Weilin Li , Ruize Wang , Gang Liang , Hao Guo","doi":"10.1016/j.mejo.2025.106697","DOIUrl":"10.1016/j.mejo.2025.106697","url":null,"abstract":"<div><div>The widespread growth of the Internet of Things (IoT) has significantly increased the need for robust data interaction mechanisms, making data security a critical challenge. Blockchain technology, characterized by its decentralized architecture, presents an innovative solution for managing data within IoT ecosystems. A collaborative cloud-edge framework emerges as a dependable option for deploying IoT blockchains; however, energy-efficient hardware support on the edge remains insufficient. To resolve this issue, this study introduces a low-power System on Chip (SoC) integrated with a specialized secure coprocessor to handle data on-chain processes. To mitigate physical-level security risks, the SoC incorporates a trusted computing architecture based on dual RISC-V cores. Experimental results using an FPGA platform reveal that the proposed SoC achieves a 12.1-fold performance enhancement for complete data on-chain processing tasks compared to the high-performance Intel i9-13950HX CPU, with total power consumption limited to just 0.579 W.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"161 ","pages":"Article 106697"},"PeriodicalIF":1.9,"publicationDate":"2025-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143887648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A process compatible SiC trench MOSFET integrated with double p+-polySi/SiC HJD for enhanced switching performance 一种工艺兼容的SiC沟槽MOSFET集成了双p+-多晶硅/SiC HJD，以增强开关性能

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-24 DOI: 10.1016/j.mejo.2025.106702

Bangmin Zhu, Jianbin Guo, Yuxing Yang, Yanghao Wang, Qingqing Sun, David Wei Zhang, Hang Xu

{"title":"A process compatible SiC trench MOSFET integrated with double p+-polySi/SiC HJD for enhanced switching performance","authors":"Bangmin Zhu, Jianbin Guo, Yuxing Yang, Yanghao Wang, Qingqing Sun, David Wei Zhang, Hang Xu","doi":"10.1016/j.mejo.2025.106702","DOIUrl":"10.1016/j.mejo.2025.106702","url":null,"abstract":"<div><div>In this article, a double polysilicon/SiC heterojunction diode (HJD) integrated SiC trench MOSFET (DHJD-TMOS) featuring an ohmic contact mesa is firstly proposed and investigated. The proposed device enables reverse current flow when the applied reverse voltage is lower than the turn-on voltage of the polysilicon/SiC HJD, achieved through precise control of the electron barrier height by optimizing the ohmic mesa width. The device architecture incorporates two key shielding features: a deep p + shield layer beneath the gate oxide and p + rings under the HJD source trenches, which collectively provide dual protection for the HJD region against high electric fields during blocking state, effectively suppressing leakage current. Comprehensive simulation results demonstrate significant performance improvements of the proposed DHJD-TMOS, including a 32 % reduction in reverse cut-in voltage and a 62 % decrease in total switching loss compared to conventional JBS-integrated MOSFETs. The high frequency figure of merits (HF-FOM) achieves an outstanding value of 64.07 mΩ⋅pF. These demonstrated device performances, as well as the good fabrication compatibility and process tolerance, making our proposed device highly attractive in future high frequency and high voltage applications.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"161 ","pages":"Article 106702"},"PeriodicalIF":1.9,"publicationDate":"2025-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143878964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A PN-complementary current-enhancement structure LDO with fast transient response and frequency compensation capability 一种具有快速瞬态响应和频率补偿能力的pn互补电流增强结构LDO

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-23 DOI: 10.1016/j.mejo.2025.106701

Sujuan Liu, Aoran Ge, Xudong Sun, Junchao Zhao, Kun Liu, Peiyuan Wan

引用次数: 0

Pocket assisted stepped tunneling to improve the band-to-band tunneling effect of nanotube TFETs 口袋辅助阶梯式隧道，改善纳米管tfet的带对带隧道效应

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-23 DOI: 10.1016/j.mejo.2025.106690

Rui Chen , Ruizhe Han , Tao Liu , Xinlong Shi , Liming Wang , Peijian Zhang , Min Xu , Huiyong Hu

{"title":"Pocket assisted stepped tunneling to improve the band-to-band tunneling effect of nanotube TFETs","authors":"Rui Chen , Ruizhe Han , Tao Liu , Xinlong Shi , Liming Wang , Peijian Zhang , Min Xu , Huiyong Hu","doi":"10.1016/j.mejo.2025.106690","DOIUrl":"10.1016/j.mejo.2025.106690","url":null,"abstract":"<div><div>This paper proposes a stepped tunneling nanotube tunnel field-effect transistor (ST-NT-TFET). By introducing a source-side doped pocket with the same polarity within the TFET channel and employing asymmetric gate bias modulation, the device transforms point tunneling into a stepped tunneling pathway, thereby enhancing the band-to-band tunneling effect. Using Si<sub>0.5</sub>Ge<sub>0.5</sub> as the source, the electrical characteristics and high-frequency performance of the ST-NT-TFET were investigated under different pocket parameters. Simulation results demonstrate that compared to conventional NT-TFETs with identical channel dimensions, the ST-NT-TFET achieves a 50% (p-TFET) and 109% (n-TFET) increase in on-state current, 92% (p) and 48% (n) enhancements in cut-off frequency, and 78% (p) and 66% boosts in gain-bandwidth product. The intrinsic delay is reduced by 55% (p) and 83% (n), while the effective drive current increases by 40% (p) and 135% (n). Circuit simulations further reveal that inverters constructed with ST-NT-TFETs exhibit a 27% increase in noise margin, 53% (fall time) and 31% (rise time) reductions in switching times, and an 11-stage ring oscillator frequency increased by 3.8 times (280% improvement).</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"162 ","pages":"Article 106690"},"PeriodicalIF":1.9,"publicationDate":"2025-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144135186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel FD-IGBT with double self-biased floating Schottky diode 一种新型双自偏置浮动肖特基二极管FD-IGBT

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-22 DOI: 10.1016/j.mejo.2025.106693

Ao Wu , Haifeng Qin , Zubing Duan , Wei Li , Li Wan , Xiandong Ma , Qiansheng Rao , Weizhong Chen

{"title":"A novel FD-IGBT with double self-biased floating Schottky diode","authors":"Ao Wu , Haifeng Qin , Zubing Duan , Wei Li , Li Wan , Xiandong Ma , Qiansheng Rao , Weizhong Chen","doi":"10.1016/j.mejo.2025.106693","DOIUrl":"10.1016/j.mejo.2025.106693","url":null,"abstract":"<div><div>This paper proposes a novel Floating Dummy IGBT (FD-IGBT) featuring integrated N- and P-type Schottky Barrier Diodes (SBDs) and investigates its performance through simulation. During the turn-on transient, hole accumulation in the floating P-base region elevates its quasi-Fermi potential, triggering the turn-on of the two series-connected SBDs and thereby clamping the voltage of the floating P-base region. This mechanism effectively reduces the Miller capacitance and significantly suppresses the reverse gate charging current from the floating P-base region to the gate. This reduces turn-on energy loss (<em>E</em><sub>ON</sub>) and improves <em>dI</em><sub>CE</sub><em>/dt</em> controllability. Under short-circuit conditions, the SBDs adaptively turn on, enhancing short-circuit tolerance time (<em>T</em><sub>SC</sub>). During turn-off state, the SBDs accelerate hole extraction, reducing turn-off time and energy loss (<em>E</em><sub>OFF</sub>). TCAD simulations show that, at the same <em>E</em><sub>ON</sub> + <em>E</em><sub>OFF</sub> (43.8 mJ/cm<sup>2</sup>), the proposed FD-IGBT reduces <em>dI</em><sub>CE</sub><em>/dt</em> by 88.2 % compared to conventional IGBTs. At the same <em>dI</em><sub>CE</sub><em>/dt</em> (2.1 kA/μs), it reduces <em>E</em><sub>ON</sub> + <em>E</em><sub>OFF</sub> by 53.4 %. Furthermore, the short-circuit withstand time (<em>T</em><sub>SC</sub>) of the proposed device is improved by 169 % compared to conventional IGBTs.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"161 ","pages":"Article 106693"},"PeriodicalIF":1.9,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143887649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An efficient surface-potential-based compact model for dynamically depleted silicon-on-insulator MOSFETs 动态耗尽绝缘体上硅mosfet的高效表面电位紧凑模型

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-22 DOI: 10.1016/j.mejo.2025.106699

Tianye Yu , Gongteng Xiao , Yudi Zhao , Guangxi Hu , Hongtao Xu , Ye Lu

{"title":"An efficient surface-potential-based compact model for dynamically depleted silicon-on-insulator MOSFETs","authors":"Tianye Yu , Gongteng Xiao , Yudi Zhao , Guangxi Hu , Hongtao Xu , Ye Lu","doi":"10.1016/j.mejo.2025.106699","DOIUrl":"10.1016/j.mejo.2025.106699","url":null,"abstract":"<div><div>This work proposes and develops a surface-potential-based compact model for dynamically depleted (DD) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs). The surface potential model is obtained by incorporating an optimized initial guess function, together with an iterative approach. Then the electric current and capacitance models are developed based on the surface potential. The compact model results are compared with both technology computer-aided design simulations and measured data from industry, good agreements are observed. The developed model can capture the hump effect in gate capacitance-voltage curves during the transition from partial depletion to full depletion regimes. Furthermore, the model can ensure symmetry and differentiability, both of which are necessary for stable convergence in circuit-level simulations. It is noted that, the model can achieve balance between accuracy and computation efficiency in the simulations. As it can describe the electric characteristics of the DD SOI MOSFETs, the model is useful for the circuit design.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"160 ","pages":"Article 106699"},"PeriodicalIF":1.9,"publicationDate":"2025-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143864436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0