Microelectronics Journal最新文献

{"title":"Multipath chopper stabilized operational amplifier with a floating high-pass filter ripple reduction loop","authors":"Inju Yu ,&nbsp;Hyungseup Kim ,&nbsp;Sanggyun Kang ,&nbsp;Mookyoung Yoo ,&nbsp;Jihyang Wi ,&nbsp;Gibae Nam ,&nbsp;Manhyeok Choi ,&nbsp;Minhyeok Son ,&nbsp;Hyoungho Ko","doi":"10.1016/j.mejo.2025.106857","DOIUrl":"10.1016/j.mejo.2025.106857","url":null,"abstract":"<div><div>This paper proposes a chopper-stabilized multipath operational amplifier with a floating high-pass filter (HPF) on the ripple rejection loop (RRL). Multipath amplifiers, combined with techniques such as chopping and auto-zeroing, effectively reduce noise and DC offset. In chopper amplifiers, high-order low-pass filters (LPFs) are commonly used to reduce output ripples, but they require a large area and limit the bandwidth. This issue can be resolved by adding an RRL to the low-frequency path (LFP). However, the RRL responds slowly to rapid changes in the common-mode voltage of the input signal. To improve this, a floating HPF is added to the RRL for faster common-mode response. The proposed amplifier is implemented in a 180-nm CMOS process with an active area of 0.95 mm², and the total current consumption is 108.7 μA with a 1.8 V supply voltage. The input-referred noise and noise efficiency factor (NEF) are 18.3 nV/√Hz and 4.17, respectively.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106857"},"PeriodicalIF":1.9,"publicationDate":"2025-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144896286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A fully pipelined, low-overhead, and energy-efficient CNN-based feature extraction accelerator for mobile visual SLAM","authors":"Bingqiang Liu ,&nbsp;Zehua Yin ,&nbsp;Ziang Duan ,&nbsp;Jian Xiao ,&nbsp;Yulong Tan ,&nbsp;Jipeng Wang ,&nbsp;Zixuan Shen ,&nbsp;Zhigang Wu ,&nbsp;Chao Wang","doi":"10.1016/j.mejo.2025.106860","DOIUrl":"10.1016/j.mejo.2025.106860","url":null,"abstract":"<div><div>Feature extraction is critical for Visual Simultaneous Localization And Mapping (VSLAM). The CNN-based SuperPoint outperforms traditional feature extractors but its high complexity hinders deployment on energy-constrained edge devices like small mobile robots. This paper proposes an energy-efficient SuperPoint hardware accelerator for VSLAM. The key contributions are: (1) developing a lightweight SuperPoint network by reducing filter numbers based on hierarchical feature characteristics, achieving an 88.3 % reduction in model size; (2) implementing a fully pipelined architecture to avoid general-purpose processing and deep learning IP, improving energy efficiency by eliminating off-chip access and sequential computation; (3) introducing a selective descriptor convolution strategy to skip redundant calculations on non-feature points, reducing descriptor computation and hardware overhead; and (4) proposing an optimized Non-Maximum Suppression strategy to remove duplicate comparisons within the sliding windows, further enhancing energy efficiency. FPGA evaluation shows 9.09 × lower hardware overhead and 58.2 mJ/frame energy efficiency, 22.2 % better than state-of-the-art, processing 480 × 640 images at 20 fps under 200 MHz.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106860"},"PeriodicalIF":1.9,"publicationDate":"2025-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144920180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 0.0013-mm2 7-bit 2-GS/s time-domain 4-bit/cycle SAR ADC with the input-recoverable constant-current VTC","authors":"Zhe Li,&nbsp;Jun Chang,&nbsp;Weimin Zhou,&nbsp;Li Dang,&nbsp;Hongzhi Liang,&nbsp;Shubin Liu","doi":"10.1016/j.mejo.2025.106855","DOIUrl":"10.1016/j.mejo.2025.106855","url":null,"abstract":"<div><div>This brief presents a high-speed compact time-domain 4-bit/cycle SAR ADC. The input voltages are converted by an input-recoverable constant-current VTC into a time difference. The time difference is digitized by an enhanced SA-Flash TDC into 4-bit per cycle. Owing to the proposed coupled capacitors in the VTC, which recover the input voltage after conversion, enabling reuse of the same VTC and TDC each SAR cycle to enhance area efficiency. A monotonous CDAC switching scheme is employed to generate voltage residue after the first cycle and accelerates the second voltage-to-time conversion by decreasing the common-mode voltage. Furthermore, the gain of VTC in the second conversion is increased to eight times that of the first conversion by adjusting the discharge current. A single-channel 7-bit 2 GS/s prototype ADC is designed and verified based on 28-nm CMOS. The core layout occupies an area of 0.0013 mm². Post-layout simulations show that SNDR and SFDR are 42.2 dB and 56.4 dB respectively at Nyquist frequency input at TT corner. The ADC consumes 6.7 mW at 0.9 V supply, achieving FoMw of 28.7 fJ/conversion-step and FoMs of 154.8 dB. From 500-point mismatch Monte Carlo simulation, SFDR above 46 dB and SNDR above 38.5 dB without calibration.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106855"},"PeriodicalIF":1.9,"publicationDate":"2025-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144908302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 5-GSPS continuous-time ΔΣ modulator with nested feedforward compensation OTA and resistive−grounded current-steering DAC achieving 225-MHz bandwidth and 68.5-dB SNR","authors":"Junyao Ji ,&nbsp;Peiyu Li ,&nbsp;Bo Wang ,&nbsp;Youxiang Chen ,&nbsp;Jie Shao ,&nbsp;Xiaojie Fan ,&nbsp;Mingyuan Ye ,&nbsp;Yan Xue ,&nbsp;Yingdan Jiang ,&nbsp;Jie Zhang ,&nbsp;Ruitao Wang ,&nbsp;Xiaofei Wang ,&nbsp;Hong Zhang","doi":"10.1016/j.mejo.2025.106854","DOIUrl":"10.1016/j.mejo.2025.106854","url":null,"abstract":"<div><div>This paper presents a 5-GSPS, 3rd-order continuous-time (CT) ΔΣ modulator in 28-nm CMOS process for wideband communications, in which operational transconductance amplifiers (OTAs) with nested feedforward compensation (NFC) and resistive-grounded current-steering DAC are proposed to address challenges of nonlinearity and thermal noise. The modulator is designed with a single-loop cascade resonator feedback (CRFB) topology to avoid signal/noise leakage issues in multistage architectures, while reference shuffling and self-timed capacitor-voltage DAC are combined to compensate the excess loop delay (ELD) with immunity to process, voltage and temperature (PVT) variations. A resistive-grounded current-steering DAC is employed in the main feedback path, which reduces thermal noise by about 30 % compared to conventional transistor-based grounding scheme. The OTA with NFC in the integrator adopts negative transconductance with neutralization capacitors to enhance the in-band gain, while an R-2R based programmable resistor structure is also employed for the integrator to realize reconfigurable system coefficients with almost constant input impedance. With a layout area of 0.35 mm², simulation results demonstrate that the CT ΔΣ modulator achieves a 68.5-dB signal-to-noise ratio (SNR), a 76.6-dB spurious-free dynamic range (SFDR), and an 11.1-bit effective number of bits (ENOB) in 225-MHz bandwidth, with 112-mW power consumption and Schreier figure-of-merit (FoMs) of 162.1-dB.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106854"},"PeriodicalIF":1.9,"publicationDate":"2025-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144903775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A CMOS rectifier with wide power dynamic range based on adaptive body bias compensation technique for radio frequency energy harvesting","authors":"Kang Zeng,&nbsp;Jian Liu,&nbsp;Rui Wang,&nbsp;Di Luo","doi":"10.1016/j.mejo.2025.106849","DOIUrl":"10.1016/j.mejo.2025.106849","url":null,"abstract":"<div><div>This paper presents a novel CMOS rectifier with wide power dynamic range (WPDR) for radio frequency energy harvesting (RFEH). In the proposed structure, an adaptive body bias compensation (ABBC) technique is employed to extend the rectifier’s power dynamic range. This is because the ABBC technique can be used to make the main rectifying transistors’ threshold voltage can be dynamically adjusted according to the input power variations. The proposed ABBC-based rectifier is equivalent to a conventional cross-coupled (CC) rectifier when the input power is low. Thus, in this case, the proposed rectifier achieves a good power conversion efficiency (PCE). On the contrary, the proposed ABBC technique can increase the threshold voltage of the main rectifying transistors when it has a high input power. Therefore, it also has a good PCE when the input power is high. For validation, we design a 433 MHz rectifier in a standard 0.13 <span><math><mi>μ</mi></math></span>m CMOS process. The post-simulated results show that it achieves a 83.6 % peak PCE and a -19.1 dBm sensitivity. Besides, its dynamic range (DR) for PCE &gt;40% and PCE&gt; 20% with a 100 k<span><math><mi>Ω</mi></math></span> load (<span><math><msub><mrow><mi>R</mi></mrow><mrow><mi>L</mi></mrow></msub></math></span>) are 15.1 dB and 26.4 dB, respectively.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106849"},"PeriodicalIF":1.9,"publicationDate":"2025-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144896284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analysis and prediction of bending-torsion coupled stress in BGA stacked solder joints considering interaction effects","authors":"Jingcheng Mo,&nbsp;Chunyue Huang,&nbsp;Chao Gao,&nbsp;Gui Wang","doi":"10.1016/j.mejo.2025.106838","DOIUrl":"10.1016/j.mejo.2025.106838","url":null,"abstract":"<div><div>A finite element model of BGA stacked solder joints was established, and finite element simulation analysis of bending-torsion coupled stress and strain was conducted. A testing platform for measuring bending-torsion coupled strain was constructed to validate the accuracy of the simulation. The solder joint diameter, pad diameter, and solder joint height were selected as influencing factors, and an orthogonal table considering the interactions between these factors was designed and established. The maximum bending-torsion coupled stress for 18 different combinations of structural parameter levels in BGA stacked solder joints was obtained, and range and variance analyses of the stress were performed. A multiple nonlinear regression prediction model for the bending-torsion coupled stress of BGA stacked solder joints was established. The results indicate that the order of influence of the factors and their interactions on the bending-torsion coupled stress of BGA stacked solder joints is as follows: solder joint diameter <span><math><mo>&gt;</mo></math></span> pad diameter <span><math><mo>&gt;</mo></math></span> solder joint height <span><math><mo>&gt;</mo></math></span> interaction between pad diameter and solder joint height <span><math><mo>&gt;</mo></math></span> interaction between solder joint diameter and solder joint height <span><math><mo>&gt;</mo></math></span> interaction between solder joint diameter and pad diameter. At a confidence level of 99%, the solder joint diameter, pad diameter, and solder joint height have a significant effect on the bending-torsion coupled stress of BGA stacked solder joints, while the interactions among these three structural parameters have an insignificant effect on the bending-torsion coupled stress. The established multiple nonlinear regression prediction model can accurately predict the bending-torsion coupled stress of BGA stacked solder joints, with a maximum error of 2.47% and an average error of 0.95% for the mathematical model.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106838"},"PeriodicalIF":1.9,"publicationDate":"2025-08-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144892870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A fully-integrated GaN driver IC with adjustable ringing suppression for LiDAR","authors":"Jilong Guo,&nbsp;Kaiyou Li,&nbsp;Jianping Guo","doi":"10.1016/j.mejo.2025.106851","DOIUrl":"10.1016/j.mejo.2025.106851","url":null,"abstract":"<div><div>—Aiming to resolve the inherent trade-off between ringing amplitude and gate edge transition rate encountered in conventional gate driver circuits, this paper presents a fully-integrated GaN gate driver IC with adjustable ringing suppression for laser detection and ranging (LiDAR) applications. The proposed solution employs a dual-channel pulse transmission architecture with a 5-bit fine-grained control of signal propagation delays, to suppress gate ringing while sustaining rapid edge transitions. Implemented in a 180-nm CMOS technology, the proposed driver IC exhibits a good balance on edge transition and overshoot voltage without any external tuning resistor. The measured edge time of the proposed driver circuit is less than 4 ns without any overshoot, which is more than 8 ns based on commercial driver IC of LMG 1025. When the edge time of the commercial counterpart is reduced to 4 ns by reducing the external tuning resistor, its overshoot is higher than 40 %. Moreover, these excellent characteristics are achieved at a lower driving current.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106851"},"PeriodicalIF":1.9,"publicationDate":"2025-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144889642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Frequency dependence of Clock-SET-induced SEU in DFF","authors":"Peipei Hao,&nbsp;Lili Ding,&nbsp;Yinhong Luo,&nbsp;Binfeng Wang,&nbsp;Yuanyuan Xue,&nbsp;Jingyan Xu,&nbsp;Tan Wang","doi":"10.1016/j.mejo.2025.106817","DOIUrl":"10.1016/j.mejo.2025.106817","url":null,"abstract":"<div><div>Though frequency dependence of static upset in a storage cell and upset caused by single-event transient (SET) in combinational logic between storage cells have been investigated extensively, there is no research on how the upset due to SET on the clock signal changes as the clock frequency increases. Using the Dynamic Dual-Copy Susceptibility Analysis and Evaluation Methodology (DDC-SAEM), the frequency dependence of single event upsets (SEUs) in D-type flip-flop (DFF) caused by SETs occurred in clock inverters or clock buffers is investigated. 80000 and 130000 random electrical simulations were made on the PMOS and NMOS transistors in the clock buffer at the 65 nm and 28 nm process nodes, respectively. Statistical results indicate that, as the clock frequency increases, clock-SET-induced SEU numbers are almost independent on the frequency at first. Then the SEU numbers increases sharply with increasing frequency, and finally the correlation curves converge. The saturation point is around 78% in the 65 nm technology and 88% in the 28 nm technology, respectively. It means that unlike the upset directly generated in the DFF, which remains relatively constant in terms of clock frequency increase and decrease, the probability of SEU induced by SETs on the clock signal is closely related to the clock frequency. When the clock frequency exceeds a certain value, the clock-SET-induced SEU will become very significant. When designing high-performance and high-reliability integrated circuits, it needs to be particularly paid attention to.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106817"},"PeriodicalIF":1.9,"publicationDate":"2025-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144908301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A gate-aware GRU model with trend-residual decomposition and quantile regression for remaining useful life prediction of IGBT","authors":"Weibo Wang ,&nbsp;Xinyu Wen ,&nbsp;Mingze Zhang ,&nbsp;Yiming Wang ,&nbsp;Yongkang Zheng ,&nbsp;Mingmao Gong ,&nbsp;Dong Liu","doi":"10.1016/j.mejo.2025.106852","DOIUrl":"10.1016/j.mejo.2025.106852","url":null,"abstract":"<div><div>In predicting the remaining useful life (RUL) of IGBT, the time series data (e.g., emitter-collector on-state voltage drop) characterizing the aging state of IGBT have the nonlinear characteristics of “slow change in the early stage and rapid degradation in the later stage”, and are accompanied by long-term trends and short-term disturbances, which bring challenges to the stability and prediction accuracy of traditional modeling methods. In addition, the existing RUL prediction models mostly focus on point prediction or parameter interval prediction based on distribution assumptions, which is difficult to meet the demand for quantification of prediction uncertainty and risk assessment in engineering applications. To this end, this paper proposes an improved gated recurrent network model (QT-GAGRU) based on trend-residual decomposition and quantile regression for realizing point-interval prediction of IGBT RUL. First, the trend and residual decomposition of the time series are performed and modeled separately using the sliding average method to alleviate the impact of data non-stationarity on the prediction performance; second, the input difference-based gate-aware mechanism (GAGRU) is introduced into the gated recurrent unit to enhance the model's ability of modeling the mutation features in the nonlinear degradation process; and then, for the first time, this paper incorporates the nonparametric interval prediction method -quartile regression (QR) is introduced into the IGBT RUL prediction model to achieve the quantification of model uncertainty without relying on distributional assumptions. Finally, the experimental results on self IGBT aging dataset and NASA public dataset show that the accuracy of the model is better than the existing IGBT RUL prediction models in terms of point prediction, and the interval prediction coverage is high and the interval width is small, which verifies the validity and engineering utility value of the QT-GAGRU model.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106852"},"PeriodicalIF":1.9,"publicationDate":"2025-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144896285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Research on the ESD characteristics of symmetric DDSCR inserted with different floating heavy dopants","authors":"Yujie Chen ,&nbsp;Yang Wang ,&nbsp;Liqiang Ding ,&nbsp;Hongjiao Yang","doi":"10.1016/j.mejo.2025.106848","DOIUrl":"10.1016/j.mejo.2025.106848","url":null,"abstract":"<div><div>—Electrostatic (ESD) protection of high-voltage chips requires a high holding voltage to prevent the latching risk. The traditional Dual-direction Slicon Controlled Rectifier (DDSCR) is a commonly used device in high-voltage ESD protection. The traditional method to increase the holding voltage (<em>V</em>_<em>h</em>) of the device involves extending its anode and cathode spacing. However, it will increase the device footprint and decrease its efficiency. To avoid using the traditional method to increase the device's holding voltage, the ESD characteristics of five symmetric DDSCR structures with different floating heavy dopants are studied. Two-dimensional device simulation, breakdown voltage, and transmission line pulse (TLP) testing were used to verify the ESD protection performance of those devices. The experimental results indicate that compared with the traditional DDSCR, the DDSCR_PN structure achieves the highest holding voltages in both forward and reverse directions, measuring 21.6 V and 27.9 V, respectively, without sacrificing its current handling capability. The intrinsic reasons for the performance of these devices are also explained in this article.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"165 ","pages":"Article 106848"},"PeriodicalIF":1.9,"publicationDate":"2025-08-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144925537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}