Microelectronics Journal最新文献_第3页

An interval-adaptive correlated multiple sampling ADC with prejudgment logic for low-noise CMOS image sensors 用于低噪声CMOS图像传感器的带预判逻辑的间隔自适应相关多采样ADC

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-06-03 DOI: 10.1016/j.mejo.2025.106720

Qiang Zhao , Shiqi Dang , Zhendong Niu , Bin Qiang , Chunhui Fan , Zhigang Li , Licai Hao , Chunyu Peng , Zhiting Lin , Xiulong Wu

{"title":"An interval-adaptive correlated multiple sampling ADC with prejudgment logic for low-noise CMOS image sensors","authors":"Qiang Zhao , Shiqi Dang , Zhendong Niu , Bin Qiang , Chunhui Fan , Zhigang Li , Licai Hao , Chunyu Peng , Zhiting Lin , Xiulong Wu","doi":"10.1016/j.mejo.2025.106720","DOIUrl":"10.1016/j.mejo.2025.106720","url":null,"abstract":"<div><div>The use of correlated multiple sampling(CMS) in CMOS image sensor(CIS) can significantly reduce the noise in readout circuits, but employing CMS leads to an increase in the conversion time and power consumption of ADC. This paper presents an interval-adaptive correlated multiple sampling ADC with prejudgment logic for low-noise CMOS image sensors. This ADC first uses a 6-bit SAR ADC to perform coarse conversion in order to choose a small-range interval, and then permits the 6-bit fine conversion to be performed only in this interval. In addition, to further reduce power consumption, prejudgment logic is used to eliminate the coarse conversion process by taking advantage of the nature of the similarity of neighboring pixel values in CIS and the structure of SAR ADC that are shared by two columns. The proposed ADC is fabricated using a 130 nm CIS process. The simulation results show that the ADC has a differential nonlinearity (DNL) of -0.75/+1 LSB, an integral nonlinearity (INL) of -1.2/+0.5 LSB, and an input referred noise of 122.5 <span><math><mi>μ</mi></math></span>Vrms , achieving a conversion time of <span><math><mrow><mn>4</mn><mo>.</mo><mn>1</mn><mspace></mspace><mi>μ</mi><mi>s</mi></mrow></math></span> in bright condition, <span><math><mrow><mn>6</mn><mo>.</mo><mn>5</mn><mspace></mspace><mi>μ</mi><mi>s</mi></mrow></math></span> in dark conditions, and the up to 20.3 % reduction in column power consumption relative to traditional CMS ADC without prejudgement logic.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"163 ","pages":"Article 106720"},"PeriodicalIF":1.9,"publicationDate":"2025-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144204898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A high power supply rejection LDO with ripple neutralization technique for Sigma-Delta D/A converter 一种用于Sigma-Delta D/A转换器的高电源抑制LDO及纹波中和技术

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-29 DOI: 10.1016/j.mejo.2025.106746

Xingyuan Tong, Zongxiang Liu, Yinbo Li, Xin Xin

引用次数: 0

Crystal plasticity finite element simulation of TSV microstructure under thermal and vibration loading 热和振动载荷下TSV显微组织的晶体塑性有限元模拟

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-29 DOI: 10.1016/j.mejo.2025.106757

Guifang Chen , Xin You , Yeting Xu , Hongjiang Qian , Peng Wang

{"title":"Crystal plasticity finite element simulation of TSV microstructure under thermal and vibration loading","authors":"Guifang Chen , Xin You , Yeting Xu , Hongjiang Qian , Peng Wang","doi":"10.1016/j.mejo.2025.106757","DOIUrl":"10.1016/j.mejo.2025.106757","url":null,"abstract":"<div><div>The reliability of through-silicon-via (TSV) microstructures for advanced packaging is crucial. Few studies address their micro-mechanical behavior under thermal cycling, vibration, and thermal-vibration coupled loading. This study uses crystal plasticity finite element method (CPFEM) to investigate plastic deformation in TSVs. Plastic work (<em>W</em><sub><em>p</em></sub>) is used as a fatigue indicator parameter (FIP) for crack initiation prediction. CPFEM simulations show thermo-mechanical coupling causes the highest <em>W</em><sub><em>p</em></sub> amplitude, reducing fatigue life in the low-cycle fatigue (LCF) regime. Vibration loading mainly leads to high-cycle fatigue (HCF) or very high-cycle fatigue (VHCF). Crack initiation patterns vary: thermal cycling and thermo-mechanical coupling cause multi-site nucleation in TSV-Cu and at interfaces, while vibration loading results in single-point initiation at interfaces. Microstructural analysis reveals thermal cycling activates slip systems at quadruple-junction grain boundaries (GBs), with stress concentrations between clustered soft grains surrounded by hard phases. Thermo-mechanical coupling initiates cracks at trident GBs due to hard grain extrusion from yielding soft phases. Interface crack locations under hybrid loading relate to the distribution of the hardest grain. These results highlight the importance of loading type and microstructure in TSV degradation, emphasizing the need for grain boundary engineering and dimensional optimization to mitigate thermo-mechanical fatigue.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"162 ","pages":"Article 106757"},"PeriodicalIF":1.9,"publicationDate":"2025-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144189874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A valley-sensed emulated peak current-mode controlled buck converter for dual-channel DDR memory systems 一种用于双通道DDR存储系统的谷感模拟峰值电流模式控制降压变换器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-29 DOI: 10.1016/j.mejo.2025.106730

Xiaopeng Diao , Zhiyong Zhu , Kaifei Fang , Hao Wen , Lishuang Lin , Ping Li , Hua Fan , Qi Wei , Quanyuan Feng

{"title":"A valley-sensed emulated peak current-mode controlled buck converter for dual-channel DDR memory systems","authors":"Xiaopeng Diao , Zhiyong Zhu , Kaifei Fang , Hao Wen , Lishuang Lin , Ping Li , Hua Fan , Qi Wei , Quanyuan Feng","doi":"10.1016/j.mejo.2025.106730","DOIUrl":"10.1016/j.mejo.2025.106730","url":null,"abstract":"<div><div>This work presents a valley-sensed emulated peak current-mode controlled buck converter specifically optimized for high-performance double data rate synchronous dynamic random access memory (DDR SDRAM) applications. In this work, a dual-channel synchronous buck converter is designed to provide a low voltage required for DDR applications. Building upon traditional emulated peak current-mode control, an innovative circuit structure with configurable pre-bias current sensing is introduced. This enhancement ensures that current sensing components are protected from high voltage stress and prevents sub-harmonic oscillations in the current sensing circuit. More importantly, it enables bidirectional switching of source and sink currents, which is essential for DDR power supply solutions. Experimental verification and testing results demonstrate that the dual-channel buck converter has an input voltage range of 3.3 V to 15 V, with a maximum output sourcing current of 6 A and a peak sinking current of 3 A. The chip is fabricated using 180 nm Bipolar-CMOS-DMOS (BCD) process technology, featuring a minimum turn-on time of 132 ns, a minimum turn-off time of 400 ns, and an operating frequency of 300 kHz. The overall chip dimensions are 2.2 mm <span><math><mo>×</mo></math></span> 3.1 mm, while the core area, excluding pads, measures 1.8 mm <span><math><mo>×</mo></math></span> 2.7 mm.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"162 ","pages":"Article 106730"},"PeriodicalIF":1.9,"publicationDate":"2025-05-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144203126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A novel minimized millimeter-wave on-chip spoof surface plasmon polariton and its applications based on IPD technology 一种新的最小化毫米波片上欺骗表面等离子激元及其基于IPD技术的应用

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-29 DOI: 10.1016/j.mejo.2025.106755

Yuyang Zeng, Yongle Wu, Yuhao Yang, Leidan Pan, Weimin Wang

引用次数: 0

On-chip integrated 0.4 GHz & 2.3 GHz Lamb wave resonators: Electrode structure optimization and flip-transfer fabrication 片上集成0.4 GHz和2.3 GHz Lamb波谐振器：电极结构优化和翻转转移制造

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-27 DOI: 10.1016/j.mejo.2025.106751

Jicong Zhao , Qiner Xu , Shitao Lv , Wenhao Ye , Qiang Xu , Yi Cao , Haiyan Sun , Jing Huang

{"title":"On-chip integrated 0.4 GHz & 2.3 GHz Lamb wave resonators: Electrode structure optimization and flip-transfer fabrication","authors":"Jicong Zhao , Qiner Xu , Shitao Lv , Wenhao Ye , Qiang Xu , Yi Cao , Haiyan Sun , Jing Huang","doi":"10.1016/j.mejo.2025.106751","DOIUrl":"10.1016/j.mejo.2025.106751","url":null,"abstract":"<div><div>—Lamb wave resonators show great potential for applications in RF filters, infrared detectors, and sensors. Converting the bottom electrode into an interdigitated-transducer (IDT) structure allows broader application. However, the piezoelectric film deposited atop patterned IDTs often suffers from poor quality and cracking, degrading or damaging resonator performance. This study presents a wafer-level flip-transfer method which flips the pre-defined piezoelectric vibration and cavity structures onto another wafer. This reversed the sequence of bottom electrode patterning and piezoelectric film deposition, avoiding the problem above. Utilizing this process, Lamb wave resonators operating at 0.4 GHz and 2.3 GHz with both IDT-IDT and IDT-Floating configurations were integrated on an 8-inch wafer. Furthermore, electrode parameters were optimized to enable the multi-mode coupling and suppress spurious signals. Test results indicate that, with 9.5 % Sc doping, Lamb wave resonators operating in the 0.4 GHz and 2.3 GHz bands achieved effective electromechanical coupling coefficients (<em>k</em><sub><em>t</em></sub><sup>2</sup>) of 2.87 % and 6.24 %, and quality factors (<em>Q</em>) of 2547 and 1332, respectively.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"162 ","pages":"Article 106751"},"PeriodicalIF":1.9,"publicationDate":"2025-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144203127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A cross-voltage-domain sub-sampling phase-locked loop operating from 6.0 GHz to 8.8 GHz 工作频率为6.0 GHz ~ 8.8 GHz的交叉电压域子采样锁相环

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-27 DOI: 10.1016/j.mejo.2025.106743

Shuai Deng , Taotao Xu , Xiang Yi , Pei Qin , Cao Wan , Chao Li , Quan Xue

{"title":"A cross-voltage-domain sub-sampling phase-locked loop operating from 6.0 GHz to 8.8 GHz","authors":"Shuai Deng , Taotao Xu , Xiang Yi , Pei Qin , Cao Wan , Chao Li , Quan Xue","doi":"10.1016/j.mejo.2025.106743","DOIUrl":"10.1016/j.mejo.2025.106743","url":null,"abstract":"<div><div>This paper presents a cross-voltage-domain sub-sampling phase-locked loop (SSPLL) operating from 6.0 GHz to 8.8 GHz, designed for compatibility with both millimeter-wave (mmWave) and C-band transceivers. Several circuit-level optimizations are applied to enhance performance and efficiency. A dual-voltage-domain architecture is adopted: digital modules operate at a lower voltage (1.2 V) for high speed and reduced power, while analog and RF modules utilize a higher voltage domain (2.5 V) to improve drive strength and noise performance. The level shifter bridges the two voltage domains, and for the first time, a comprehensive analysis of its phase noise performance is presented, providing key insights to prevent SSPLL phase noise degradation. An input divide-by-2 enhances output frequency resolution. A class-C voltage-controlled oscillator (VCO) is adopted to reduce power consumption. The PLL is implemented in a 65 nm CMOS process, occupying a core area of 0.346 mm<sup>2</sup>. The VCO covers a frequency range of 5.98–8.83 GHz. This PLL achieves a root-mean-square (rms) jitter of 500 fs integrated from 10 kHz to 100 MHz with a typical power consumption of 43.6 mW. A reference spur of −55.42 dBc is measured with the PLL operating at 7.8 GHz.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"163 ","pages":"Article 106743"},"PeriodicalIF":1.9,"publicationDate":"2025-05-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144212203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An ultra-low-power CMOS image sensor with a new pixel structure in PWM mode featuring a programmable ramp generator for calibration 一种超低功耗CMOS图像传感器，具有PWM模式下的新像素结构，具有可编程斜坡发生器用于校准

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-23 DOI: 10.1016/j.mejo.2025.106726

Ziyuan Wang, Ye Zhao, Aoming Zhan, Jinyu Gao, Long Chen, Cunbiao Hao, Hongying Zhang, Shushan Qiao

{"title":"An ultra-low-power CMOS image sensor with a new pixel structure in PWM mode featuring a programmable ramp generator for calibration","authors":"Ziyuan Wang, Ye Zhao, Aoming Zhan, Jinyu Gao, Long Chen, Cunbiao Hao, Hongying Zhang, Shushan Qiao","doi":"10.1016/j.mejo.2025.106726","DOIUrl":"10.1016/j.mejo.2025.106726","url":null,"abstract":"<div><div>This paper presents an ultra-low-power 128 × 128 pixel pulse-width modulation (PWM) CMOS image sensor for low power applications. For always-on ultra-low-power imaging, a novel PWM pixel circuit with a tapered reset technology is implemented. Additionally, by turning off all the pixels except those in reset phase and readout phase, power consumption is reduced from 52 nW to 0.1 nW for each pixel. In addition, to overcome the settling latency of subthreshold comparator, we use a programmable ramp generator for voltage-to-time conversion for linear response, achieving a non-linearity of 0.04%. This ultra-low-power CMOS image sensor is designed and fabricated in CMOS 180 nm process technology. Measurement results demonstrate that the proposed CMOS image sensor consumes only <span><math><mrow><mn>61</mn><mo>.</mo><mn>6</mn><mspace></mspace><mi>μ</mi><mi>W</mi></mrow></math></span> at 62.5 frames per second (fps) with a fill factor of 58% at 0.8V operation. These performances make the image sensor perfectly suitable for IoT applications and some other edge devices.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"162 ","pages":"Article 106726"},"PeriodicalIF":1.9,"publicationDate":"2025-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144147930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 8–10 GHz compact low noise amplifier MMIC with high linearity based on GaAs technology 一种基于GaAs技术的8-10 GHz高线性度紧凑型低噪声MMIC放大器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-23 DOI: 10.1016/j.mejo.2025.106742

Xuejie Bai, Yongle Wu, Shuchen Zhen, Zhenxing Gao, Weimin Wang

引用次数: 0

Optimizing label correlation in deep learning-based side-channel analysis 基于深度学习的边信道分析中标签相关性的优化

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-05-23 DOI: 10.1016/j.mejo.2025.106721

Shengcheng Xia, Lang Li, Yu Ou, Jiahao Xiang

{"title":"Optimizing label correlation in deep learning-based side-channel analysis","authors":"Shengcheng Xia, Lang Li, Yu Ou, Jiahao Xiang","doi":"10.1016/j.mejo.2025.106721","DOIUrl":"10.1016/j.mejo.2025.106721","url":null,"abstract":"<div><div>Label distribution learning techniques can significantly enhance the effectiveness of side-channel analysis. However, this method relies on using probability density functions to estimate the relationships between labels. The settings of parameters play a crucial role in the impact of the attacks. This study introduces a non-parametric statistical method to calculate the distribution between labels, specifically employing smoothing with the Gaussian kernel function and adjusting bandwidth. Then, the aggregation of the results from each label processed by the Gaussian kernel facilitates a hypothesis-free estimation of the label distribution. This method accurately represents the actual leakage distribution, speeding up guess entropy convergence. Secondly, we exploit similarities between profiling traces, proposing an analysis scheme for sample correlation locally of label distribution learning. Furthermore, Signal to-Noise Ratio (SNR) is employed to re-extract and reduce dataset dimensions to 500 power consumption points, resulting in noise reduction. Our results showcase the successful training of 800 profiling traces using our method for sample correlation locally of label distribution learning, with the findings indicating its exceptional performance.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"162 ","pages":"Article 106721"},"PeriodicalIF":1.9,"publicationDate":"2025-05-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144135185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0