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DC and RF analysis of ScAlN/GaN/β-Ga2O3 and ScAlN/InGaN/GaN/β-Ga2O3 HEMTs on SiC substrate SiC衬底上ScAlN/GaN/β-Ga2O3和ScAlN/InGaN/GaN/β-Ga2O3 HEMT的直流和射频分析
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-08-31 DOI: 10.1016/j.mejo.2024.106394
{"title":"DC and RF analysis of ScAlN/GaN/β-Ga2O3 and ScAlN/InGaN/GaN/β-Ga2O3 HEMTs on SiC substrate","authors":"","doi":"10.1016/j.mejo.2024.106394","DOIUrl":"10.1016/j.mejo.2024.106394","url":null,"abstract":"<div><p>Scandium aluminum nitride (Sc<sub>x</sub>Al<sub>1-x</sub>N) is a promising material among group III nitrides, offering outstanding polarization properties resulting in very large carrier densities. We report the comparative analysis of Sc<sub>0.18</sub>Al<sub>0.72</sub>N/GaN/β-Ga<sub>2</sub>O<sub>3</sub> and Sc<sub>0.18</sub>Al<sub>0.72</sub>N/InGaN/GaN/β-Ga<sub>2</sub>O<sub>3</sub> HEMTs on Silicon carbide substrate. L<sub>G</sub> = 55 nm, Sc<sub>0.18</sub>Al<sub>0.72</sub>N/GaN/β-Ga<sub>2</sub>O<sub>3</sub> HEMT demonstrated maximum current density (I<sub>DS</sub>) of 4.38 A/mm, very large carrier density (n<sub>s</sub>) of 2.34 × 10<sup>13</sup> cm<sup>−2</sup>, large breakdown voltage (74 V) with low on-resistance (R<sub>on</sub> ∼ 0.2 Ω mm), and cut-off frequency (f<sub>T</sub>)/maximum oscillation frequency (f<sub>max</sub>) of 220/242 GHz. Introduction of a very thin 5 nm In<sub>0.1</sub>Ga<sub>0.9</sub>N layer in the channel, further improves the 2DEG (two-dimensional electron density), drain current, breakdown voltage. Furthermore, Sc<sub>0.18</sub>Al<sub>0.72</sub>N/InGaN/GaN/β-Ga<sub>2</sub>O<sub>3</sub> heterostructure shows stable transconductance (g<sub>m</sub>) over wide gate bias. A gate voltage swing (GVS) of 7.72, I<sub>DS</sub> of 6.08 A/mm, and V<sub>BR</sub> of 105 V with R<sub>on</sub> ∼ 0.138 recorded. These findings show the merits of scandium aluminium nitride barrier material, which enables the HEMTs for next generation radar and telecommunications.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142148469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 28-47.5 GHz broadband power amplifier using improved MCR technique in 40-nm CMOS 采用改进型 MCR 技术的 40 纳米 CMOS 28-47.5 GHz 宽带功率放大器
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-08-30 DOI: 10.1016/j.mejo.2024.106395
{"title":"A 28-47.5 GHz broadband power amplifier using improved MCR technique in 40-nm CMOS","authors":"","doi":"10.1016/j.mejo.2024.106395","DOIUrl":"10.1016/j.mejo.2024.106395","url":null,"abstract":"<div><p>This paper presents a broadband power amplifier (PA) implemented in 40-nm CMOS process for low power application. The PA cascades two stages of common-source differential transistors and adopts symmetrical magnetically coupled resonators (MCRs) for impedance matching and single-ended differential conversion. Theoretical analysis elucidates the effect of the resonator <em>Q</em> on the frequency response of the transformer, thus giving the distribution of the poles and their precise locations, and revealing the quantitative relationship between bandwidth and gain ripple. A method for efficiently balancing gain ripple and bandwidth in <em>k</em>, <em>Q</em> space under low-power conditions when the intrinsic <em>Q</em> of the source impedance is high is described in detail. Measurement results demonstrate a 51.6% 3-dB bandwidth from 28 to 47.5 GHz. The PA achieve 10.7 dBm P<span><math><msub><mrow></mrow><mrow><mi>sat</mi></mrow></msub></math></span>, 8.5 dBm OP<span><math><msub><mrow></mrow><mrow><mi>1db</mi></mrow></msub></math></span> and 23% peak PAE at 31 GHz.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142122601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Piezoelectric-electromagnetic collaborative energy extraction circuit for wearable vibration energy harvester 用于可穿戴振动能量收集器的压电电磁协同能量提取电路
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-08-29 DOI: 10.1016/j.mejo.2024.106376
{"title":"Piezoelectric-electromagnetic collaborative energy extraction circuit for wearable vibration energy harvester","authors":"","doi":"10.1016/j.mejo.2024.106376","DOIUrl":"10.1016/j.mejo.2024.106376","url":null,"abstract":"<div><p>A piezoelectric-electromagnetic collaborative energy extraction circuit (PEC-EC) is presented in this paper to extract low-frequency vibration energy from arm swinging for wearable devices. This circuit simultaneously harvests energy from both the piezoelectric transducer (PZT) and electromagnetic coil generator (ECG). When the piezoelectric output voltage reaches its peak, the peak detection circuit becomes conductive, and the energy of the piezoelectric material is extracted at this moment. At the same time, the PEC-EC circuit can also harvest electromagnetic energy. Especially, even at low electromagnetic voltage input, the electromagnetic voltage can be extracted through the designed switch. The experimental results show that the circuit starts up only when the input voltage reaches 0.5V. The electromagnetic energy conversion efficiency can reach 53 %, and the piezoelectric energy conversion efficiency can reach 56 %. The effectiveness of collaborative extraction was also verified through experimental validation.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142122600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Hourglass transistor: An alternative and improved MOS structure robust to total ionization dose radiation 沙漏晶体管一种可抵御全电离剂量辐射的替代性改进 MOS 结构
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-08-26 DOI: 10.1016/j.mejo.2024.106391
{"title":"Hourglass transistor: An alternative and improved MOS structure robust to total ionization dose radiation","authors":"","doi":"10.1016/j.mejo.2024.106391","DOIUrl":"10.1016/j.mejo.2024.106391","url":null,"abstract":"<div><p>This paper presents a novel MOSFET layout named the “hourglass transistor”, aimed to improve its electrical behavior under Total Ionizing Dose (TID) effects. The new radiation-tolerant device is based on augmenting parasitic channel resistance, alteration of the electric field by the longitudinal corner effect (LCE), and reducing channel resistance within the central gate region. The radiation-robust MOS structure design was implemented in a 130 nm CMOS bulk process and its performance was analyzed through simulations using 3D physical models. The proposed hourglass transistor was compared with rectangular, diamond, dog bone and H-gate devices, showing a reduction in the post-radiation <span><math><msub><mrow><mi>I</mi></mrow><mrow><mi>o</mi><mi>f</mi><mi>f</mi></mrow></msub></math></span> current of 8.77, 4.6, 1.85 and 13.7 times, respectively; and a pre-radiation normalized saturation current of 2.29, 1.04, 1.58 and 1.52 times greater with an increase of 4.84, 1, 2.47 and 2.03 times the gate area, respectively.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142097739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impacts of quantum confinement effect on threshold voltage and drain-induced barrier lowering effect of junctionless surrounding-gate nanosheet NMOSFET including source/drain depletion regions 量子约束效应对包含源极/漏极耗尽区的无结环绕栅纳米片 NMOSFET 的阈值电压和漏极诱导的势垒降低效应的影响
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-08-26 DOI: 10.1016/j.mejo.2024.106392
{"title":"Impacts of quantum confinement effect on threshold voltage and drain-induced barrier lowering effect of junctionless surrounding-gate nanosheet NMOSFET including source/drain depletion regions","authors":"","doi":"10.1016/j.mejo.2024.106392","DOIUrl":"10.1016/j.mejo.2024.106392","url":null,"abstract":"<div><p>In order to modeling of junctionless (JL) surrounding-gate (SG) nanosheet MOSFET more accurately, a new model for determining threshold voltage and drain-induced barrier lowering (DIBL) effect of JL SG nanosheet NMOSFET is proposed through deriving the Poisson's equation under rectangular coordinate system. The model captures quantum confinement effect and source/drain depletion regions, it is validated through the Sentaurus TCAD simulation results. Variations of source/drain depletion regions with the channel width, height, doping concentration, the gate bias, the drain bias and variations of threshold voltage, DIBL with the channel width, height, doping concentration considering and not considering quantum confinement effect are studied, respectively. The results show influences of quantum confinement effect on source/drain depletion regions, threshold voltage and DIBL. The developed model will offer quantum corrections in JL SG nanosheet NMOSFET.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142086903","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A power-efficient, single-phase, contention-free flip-flop with only three clock transistors 仅有三个时钟晶体管的高能效、单相、无争用触发器
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-08-26 DOI: 10.1016/j.mejo.2024.106390
{"title":"A power-efficient, single-phase, contention-free flip-flop with only three clock transistors","authors":"","doi":"10.1016/j.mejo.2024.106390","DOIUrl":"10.1016/j.mejo.2024.106390","url":null,"abstract":"<div><p>Flip-flop research in recent years has been motivated by power- and/or energy-efficient designs. Flip-flop power is based on data activity (DA), which in many applications ranges from 5 to 15%. In such cases, a substantial amount of clock power and energy is wasted. In this paper, a power-efficient, contention-free flip-flop with only three single-phase clock transistors is proposed, which has low-power consumption and eliminates unnecessary internal transitions in the circuit. This flip-flop is referred as 3CTSPC. Test-chip measurement results show that at VDD = 1 V, CK = 25 MHz, and DA = 12.5%, 3CTSPC is 11% and 58% more power-efficient than 18TSPC and TGFF, respectively.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://www.sciencedirect.com/science/article/pii/S1879239124000948/pdfft?md5=96b5bbe7d673463a2631643d5ceaa032&pid=1-s2.0-S1879239124000948-main.pdf","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142098071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel narrowband MEMS filter with extensional mode resonators 采用扩展模式谐振器的新型窄带 MEMS 滤波器
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-08-25 DOI: 10.1016/j.mejo.2024.106393
{"title":"A novel narrowband MEMS filter with extensional mode resonators","authors":"","doi":"10.1016/j.mejo.2024.106393","DOIUrl":"10.1016/j.mejo.2024.106393","url":null,"abstract":"<div><p>This work proposes a novel electrostatic mechanically coupled narrowband filter based on width extensional mode (WEM) resonators. Rectangle plate WEM resonators have the potential for high quality factor (<em>Q</em>) and low motional resistance. The rectangle plate was slotted to reduce thermoelastic loss and optimize mode shape coefficient of WEMs. The <em>Q</em> values of coupled WEM resonators exceed 80,000, enabling a narrow bandwidth filter. A 3<em>λ</em>/4-length coupling beam filter (CBF) was demonstrated. The 3<em>λ</em>/4 coupling beam filter has a center frequency of 79.79 MHz and a bandwidth of 0.024 %. The CBF exhibits an impressive 26.39 dB stopband rejection and 6.97 dB insertion loss with 5.13 dB passband ripple. The MEMS filters presented in this work hold significant potential for applications in wireless communication systems.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142086902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Expanding the dose window of step-etched space-modulated JTE for ultrahigh voltage 4H-SiC devices 为超高电压 4H-SiC 器件扩展阶跃蚀刻空间调制 JTE 的剂量窗口
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-08-25 DOI: 10.1016/j.mejo.2024.106387
{"title":"Expanding the dose window of step-etched space-modulated JTE for ultrahigh voltage 4H-SiC devices","authors":"","doi":"10.1016/j.mejo.2024.106387","DOIUrl":"10.1016/j.mejo.2024.106387","url":null,"abstract":"<div><p>A step-etched space-modulated junction termination extension (SE-SM-JTE) is proposed for ultrahigh voltage (≥10 kV) 4H-SiC devices in this work. The proposed structure creates a stepped effective JTE dose profile by introducing the step etching into space-modulated JTE (SM-JTE), which shows great merits in the compromises of the JTE dose window, termination efficiency, termination area, and the complexity of the fabrication process. According to the TCAD simulation results, the SE-SM-JTE with a length of 300 μm (3 times the drift layer thickness) obtains a wide implantation dose window of ±47 % above 12 kV, achieving a wide tolerance to JTE dose and surface fixed charge. The maximum breakdown voltage (BV) of the proposed SE-SM-JTE is 13.8 kV, exhibiting a termination efficiency of 92 %. Moreover, the proposed JTE structure requires only a single ion implantation and subsequent two etchings, which facilitates the fabrication feasibility in ultrahigh voltage 4H-SiC devices.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142058150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1 V supply 10.3 ppm/°C 59 nW subthreshold CMOS voltage reference A 1 V 电源 10.3 ppm/°C 59 nW 亚阈值 CMOS 电压基准
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-08-24 DOI: 10.1016/j.mejo.2024.106389
{"title":"A 1 V supply 10.3 ppm/°C 59 nW subthreshold CMOS voltage reference","authors":"","doi":"10.1016/j.mejo.2024.106389","DOIUrl":"10.1016/j.mejo.2024.106389","url":null,"abstract":"<div><p>—A low temperature coefficient (TC), low power subthreshold CMOS voltage reference (CVR) over a wide temperature range is presented in this paper. The proposed circuit employs the voltage difference between the two inputs of the operational amplifier as the proportional to absolute temperature (PTAT) voltage and the complementary to absolute temperature (CTAT) voltage, which is obtained by the <span><math><mrow><mo>Δ</mo><msub><mi>V</mi><mtext>GS</mtext></msub></mrow></math></span> of different-threshold transistors biased in the subthreshold region. The proposed CVR was designed in the 0.18-μm CMOS process with a total area of 0.0049 mm<sup>2</sup>. It achieves an average temperature coefficient (TC) of 10.3 ppm/°C over a temperature range of −40 °C–120 °C, with a TC of 4.9 ppm/°C at the TT corner. The measured power supply rejection ratio (PSRR) is −65 dB at 10 Hz and −30 dB at 1 MHz, while the power consumption is 59 nW at a supply voltage of 1 V. The average line sensitivity (LS) is 0.16 %/V, and the LS is 0.09 %/V at the TT corner.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142084238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A reconfigurable FPGA-based spiking neural network accelerator 基于 FPGA 的可重构尖峰神经网络加速器
IF 1.9 3区 工程技术
Microelectronics Journal Pub Date : 2024-08-23 DOI: 10.1016/j.mejo.2024.106377
{"title":"A reconfigurable FPGA-based spiking neural network accelerator","authors":"","doi":"10.1016/j.mejo.2024.106377","DOIUrl":"10.1016/j.mejo.2024.106377","url":null,"abstract":"<div><p>The spiking neural network (SNN) is suitable for the intelligent edge computing applications because of its low-power characteristic. This work designs a reconfigurable spiking neural network accelerator supporting the spatiotemporal backpropagation (STBP) training method. The reconfigurable architecture is proposed between the spatial convolution module and the temporal accumulation module of the SNN accelerator. A sparse zero-hopping mechanism is designed to exploit the input sparsity of SNN datasets, and a mask mechanism is introduced between the forward inference computation and the backward training computation to exploit the output sparsity. During the training process, the peak and average performances of the SNN accelerator are 5.57 TOPS and 4.96 TOPS respectively, the power consumption is 6.124 W and the energy efficiency is 0.81 TOPS/W. The peak and average performances of the SNN accelerator are 5.98 TOPS and 5.14 TOPS respectively, the power consumption is 6.943 W and the energy efficiency is 0.74 TOPS/W, during the inference process.</p></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142075989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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