Microelectronics Journal最新文献_第3页

Hydrogen and oxygen induced abnormal reliability degradation in flexible top-gate amorphous In-Ga-Zn-O thin-film transistors under negative bias thermal illumination stress 在负偏置热照明应力下，氢氧诱导柔性顶栅非晶in- ga - zn - o薄膜晶体管可靠性异常退化

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-09-17 DOI: 10.1016/j.mejo.2025.106902

Dongbhin Kim , Kyeong-Bae Lee , Byoungdeog Choi

{"title":"Hydrogen and oxygen induced abnormal reliability degradation in flexible top-gate amorphous In-Ga-Zn-O thin-film transistors under negative bias thermal illumination stress","authors":"Dongbhin Kim , Kyeong-Bae Lee , Byoungdeog Choi","doi":"10.1016/j.mejo.2025.106902","DOIUrl":"10.1016/j.mejo.2025.106902","url":null,"abstract":"<div><div>Ensuring device stability under various stress factors is critical for the long-term operation of flexible amorphous InGaZnO thin-film transistors (a-IGZO TFTs) for market-ready display applications. Here, we report the abnormal threshold voltage (<em>V</em><sub>th</sub>) shift behavior in flexible top-gate a-IGZO TFTs under negative-bias temperature illumination stress (NBTIS). Under NBTIS, an initial negative <em>V</em><sub>th</sub> shift occurred. However, with an extended stress duration, an unexpected positive <em>V</em><sub>th</sub> shift occurred, deviating from the expected charge-trapping model. Our results show that this phenomenon is strongly correlated with the thickness of the a-IGZO active layer, with thicker films exhibiting more pronounced reverse <em>V</em><sub>th</sub> shifts. Photo-excited charge collection spectroscopy and X-ray photoelectron spectroscopy analyses revealed that the density of hydrogen/oxygen-related defect states near the valence band maximum increased with increasing a-IGZO thickness, facilitating the enhanced photo and thermal excitation of charge carriers under illumination and thermal stresses. We demonstrate that the optimization of the a-IGZO channel thickness can effectively suppress the observed abnormal reliability degradation under NBTIS, providing valuable insights into optimizing a-IGZO TFTs for enhanced long-term stability in next-generation flexible and transparent electronic applications.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"166 ","pages":"Article 106902"},"PeriodicalIF":1.9,"publicationDate":"2025-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145107101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A reliability-noise-delay quantification method for APUF physical modeling and CRPs screening 一种用于APUF物理建模和crp筛选的可靠性-噪声-延迟量化方法

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-09-17 DOI: 10.1016/j.mejo.2025.106895

Zhengfeng Huang , Ruixiang Liu , Zezheng Wang , Yanrong Zhu , Jingchang Bian , Zhao Yang , Yingchun Lu , Yiming Ouyang , Huaguo Liang , Tianming Ni

{"title":"A reliability-noise-delay quantification method for APUF physical modeling and CRPs screening","authors":"Zhengfeng Huang , Ruixiang Liu , Zezheng Wang , Yanrong Zhu , Jingchang Bian , Zhao Yang , Yingchun Lu , Yiming Ouyang , Huaguo Liang , Tianming Ni","doi":"10.1016/j.mejo.2025.106895","DOIUrl":"10.1016/j.mejo.2025.106895","url":null,"abstract":"<div><div>Arbiter Physical Unclonable Functions (APUFs), widely used strong PUFs, are highly sensitive to environmental noise, yet the quantitative link between noise and reliability remains unclear. This paper introduces a Reliability-Noise-Delay (RND) quantification method grounded in statistical analysis of the APUF delay model. By modeling noise, we uncover CRP instability patterns under varying noise levels and derive a closed-form relationship between reliability and noise. Leveraging RND, the delay difference between last-stage paths is calculated without extra hardware by using environmental noise measurements and CRP reliability. We develop an efficient n-stages APUF modeling approach requiring only n+1 CRPs with known reliability, significantly reducing computational complexity and resource demands compared to conventional machine-learning techniques. Furthermore, we propose a screening strategy to identify high- and low-reliability CRPs: at a noise level of 0.15, low-reliability CRP reliability drops from 75 % (random) to 57 %, while high-reliability CRPs reach 99 %. Our method offers an effective tool for APUF modeling and optimization in noisy environments.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"166 ","pages":"Article 106895"},"PeriodicalIF":1.9,"publicationDate":"2025-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145158629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A multi-channel OOK/BFSK transmitter with FoM of 99.99/91.2 and HD3/5 <−40 dBc 一种多通道OOK/BFSK发射机，FoM为99.99/91.2,HD3/5 <−40 dBc

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-09-16 DOI: 10.1016/j.mejo.2025.106875

Shiwei Li , Jiwei Huang

{"title":"A multi-channel OOK/BFSK transmitter with FoM of 99.99/91.2 and HD3/5 <−40 dBc","authors":"Shiwei Li , Jiwei Huang","doi":"10.1016/j.mejo.2025.106875","DOIUrl":"10.1016/j.mejo.2025.106875","url":null,"abstract":"<div><div>A 423.5–450 MHz low-power OOK/BFSK wireless transmitter (TX) is presented for biomedical applications. The TX utilizes injection locking, frequency multiplication, and harmonic rejection techniques. A frequency synthesizer based on low-frequency phase rotation enables multi-channel support and BFSK modulation. High-frequency quantization noise introduced by the delta-sigma modulator (DSM) is filtered out using an N-path filter and dual multi-phase injection-locked ring oscillators (ILROs). Finally, a harmonic-rejection edge combiner (HREC) is used to achieve 5X frequency multiplication, effectively lowering the operating frequency of other circuits and significantly reducing the system’s power consumption. The HREC provides rejection of the <span><math><mrow><mn>3</mn><mi>rd</mi></mrow></math></span>/<span><math><mrow><mn>5</mn><mi>th</mi></mrow></math></span> harmonics while generating the desired carrier frequency. The TX is designed using a 65 nm CMOS process with a core area of 0.0625 <span><math><msup><mrow><mi>mm</mi></mrow><mrow><mn>2</mn></mrow></msup></math></span>. The simulation results show that the TX consumes 985 <span><math><mi>μ</mi></math></span>W at 1 V supply voltage and can provide −6.62 dBm output power to a <span><math><mrow><mn>50</mn><mspace></mspace><mi>Ω</mi></mrow></math></span> load without any on-chip or off-chip inductance, which reduces the chip area. The TX achieves <span><math><mo><</mo></math></span>−40 dBc rejection for both <span><math><mrow><mn>3</mn><mi>rd</mi></mrow></math></span> and <span><math><mrow><mn>5</mn><mi>th</mi></mrow></math></span> harmonics, supports data rates of 45/6 Mbps under OOK/BFSK modulation, respectively, achieving energy efficiency of 21.8/164 pJ/bit and FoM of 99.99/91.2.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"166 ","pages":"Article 106875"},"PeriodicalIF":1.9,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145159420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An efficient PEH Pseudo-MPPT rectifier using a combination of an enhanced Sense and Set and improved FNOV schemes 一种高效的PEH伪mppt整流器，结合了增强的Sense和Set和改进的FNOV方案

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-09-16 DOI: 10.1016/j.mejo.2025.106891

Saman Shoorabi Sani

{"title":"An efficient PEH Pseudo-MPPT rectifier using a combination of an enhanced Sense and Set and improved FNOV schemes","authors":"Saman Shoorabi Sani","doi":"10.1016/j.mejo.2025.106891","DOIUrl":"10.1016/j.mejo.2025.106891","url":null,"abstract":"<div><div>— Even though a <em>Maximum Power Point Tracking (MPPT)</em>-based <em>Piezoelectric Energy Harvester (PEH) Interface Circuit (PEHIC)</em> may improve energy extraction, complex trade-offs between <em>Converter Efficiency</em>, <em>MPPT Efficiency</em>, and <em>Duty-Cycling Efficiency</em> mean that complicated <em>MPPT</em> schemes do not always increase the <em>End-To-End Efficiency</em>. This study investigates these complexities and introduces a balanced solution for <em>Vibration Energy Scavenging</em>.</div><div>1The proposed circuit periodically <em>Senses</em> and <em>Sets</em> an adjustable approximation of the <em>Maximum Power Point Voltage</em>, <em>V</em><sub><em>mpp</em></sub><em>,</em> called <em>V</em><sub><em>pseudo-mpp</em></sub>, instead of the fixed <em>V</em><sub><em>oc,max</em></sub><em>/2</em> used in standard <em>Maximum Power Point Sensing (MPPSn)</em>. A <em>Pseudo-MPPT</em> scheme utilizing a <em>Fractional Normal Operation Voltage (FNOV)</em> method operates as a non-interrupted <em>MPPSn</em> via a novel pre-sampling scheme, relaxed <em>Maximum Power Point Setting (MPPSt)</em> procedure, and highly efficient circuitry to increase <em>Converter Efficiency</em>. The <em>End-To-End Efficiency (η</em><sub><em>End-To-End</em></sub><em>)</em> reaches ∼0.52, and for the same input, the proposed circuit extracts 4.6 × more power than a <em>Standard Energy Harvesting (SEH)</em> circuit.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"166 ","pages":"Article 106891"},"PeriodicalIF":1.9,"publicationDate":"2025-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145107100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A QNU hardened latch design with low cost high stability and high performance 一种低成本、高稳定性和高性能的QNU硬化闩锁设计

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-09-15 DOI: 10.1016/j.mejo.2025.106896

Zhengfeng Huang , Xinyu Jiang , Linya Qiu , Yuxin Zhu , Can Liu , Huaguo Liang , Yiming Ouyang , Tianming Ni

引用次数: 0

A 4.5 mW 58.7 dB SNDR discrete-time delta–sigma modulator based on MOTFTs for ECG signal recording 基于mofts的4.5 mW 58.7 dB SNDR离散时间δ - σ调制器用于心电信号记录

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-09-13 DOI: 10.1016/j.mejo.2025.106877

Zhaoyu Deng, Rongsheng Chen, Delang Lin, Zhaohui Wu, Bin Li, Mingjian Zhao

引用次数: 0

A BVD-based on-chip bandpass filter with simplified source-load coupling for 5G N77 band using HRS IPD technology 一种基于bvd的片上带通滤波器，采用HRS IPD技术，简化了5G N77频段的源负载耦合

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-09-12 DOI: 10.1016/j.mejo.2025.106893

Yuhan Cao, Bukun Xu, Bo Yuan, Gaofeng Wang

{"title":"A BVD-based on-chip bandpass filter with simplified source-load coupling for 5G N77 band using HRS IPD technology","authors":"Yuhan Cao, Bukun Xu, Bo Yuan, Gaofeng Wang","doi":"10.1016/j.mejo.2025.106893","DOIUrl":"10.1016/j.mejo.2025.106893","url":null,"abstract":"<div><div>This letter presents a compact on-chip N77 band filter exhibiting high rejection and low insertion loss. A novel design method is proposed to enhance the performance of lumped-element circuits through the analysis of bulk acoustic wave (BAW) resonators. First, the resonant and anti-resonant frequencies of the BAW resonator are optimally designed based on N77 band specifications. We then integrate the resonator in parallel with a simplified source-load coupling network. This integration significantly improves low-end rejection. It also maintains low insertion loss. Following capacitance adjustment, the resonator is replaced with an equivalent Butterworth–Van Dyke (BVD) model, enabling wider resonator bandwidth and effective spurious signal rejection. Analysis of S-parameter magnitude/phase and admittance elucidates the source-load coupling mechanism, which generates transmission zeros (TZs) at both passband edges, thus enhancing selectivity. The filter is fabricated using high-resistivity silicon (HRS) IPD technology. It achieves a compact size of 1.3 × 0.7 mm<sup>2</sup>. Measurement results show an insertion loss of less than 1.7 dB. The relative bandwidth exceeds 61.3 % across the passband.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"166 ","pages":"Article 106893"},"PeriodicalIF":1.9,"publicationDate":"2025-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145107174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Performance analysis of dual stacked DRAM for low power embedded devices 低功耗嵌入式器件双堆叠DRAM性能分析

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-09-11 DOI: 10.1016/j.mejo.2025.106890

Rupesh Narayan , Rishu Kumar , Abhishek Raj , Shashi Kant Sharma

{"title":"Performance analysis of dual stacked DRAM for low power embedded devices","authors":"Rupesh Narayan , Rishu Kumar , Abhishek Raj , Shashi Kant Sharma","doi":"10.1016/j.mejo.2025.106890","DOIUrl":"10.1016/j.mejo.2025.106890","url":null,"abstract":"<div><div>This work presents a novel dual-stacked silicon/SiGe-based DRAM architecture intended to overcome the constraints of conventional DRAM like scaling, high refresh power and charge leakage. Two vertically stacked layers of silicon and silicon-germanium (SiGe) with 40 % Ge content have been used in the proposed structure to maximize band-to-band tunnelling (BTBT) that has resulted in improved charge storage and retention without the necessity of a large capacitor. Channel engineering of SiGe area in the proposed structure has considerably enhanced the tunnelling rate that has resulted in faster and more effective write and hold operations. Enhanced read reliability is confirmed by a notable sense margin of 6.61 × 10<sup>-</sup><sup>6</sup> A/μm and retention time of approximately 500 ms. The proposed small, capacitorless and energy-efficient DRAM design has successfully demonstrated all the basic DRAM operations like Write '1′, Hold '1′, Read '1′ to verify logic high and then Write '0′, Hold '0′, Read '0′ to confirm logic low, for next generation low power embedded applications.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"166 ","pages":"Article 106890"},"PeriodicalIF":1.9,"publicationDate":"2025-09-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145061082","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator 一个56 Gb/s的PAM4斜率采样CDR，带同步四输出相位插值器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-09-10 DOI: 10.1016/j.mejo.2025.106872

Zekai Yang , Xiaoteng Zhao , Huajin Sun , Xianting Su , Zhicheng Dong , Yilong Dong , Yukui Yu , Hongzhi Liang , Shubin Liu

引用次数: 0

A 0.029-mm2 11.5-ENOB 8.05-kHz BW voltage Fold-Shrink SAR ADC for cochlear implant 一种用于人工耳蜗的0.029 mm2 11.5-ENOB 8.05 khz BW电压折叠收缩SAR ADC

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-09-10 DOI: 10.1016/j.mejo.2025.106885

Hongbo Gu , Wei Zhang , Lei Liao , Zhihui Qin

{"title":"A 0.029-mm2 11.5-ENOB 8.05-kHz BW voltage Fold-Shrink SAR ADC for cochlear implant","authors":"Hongbo Gu , Wei Zhang , Lei Liao , Zhihui Qin","doi":"10.1016/j.mejo.2025.106885","DOIUrl":"10.1016/j.mejo.2025.106885","url":null,"abstract":"<div><div>This work introduces a voltage Fold-Shrink Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). It is characterized by an all-resistor divider Digital-to-Analog Converter (DAC) which keeps a proportional voltage for the Most Significant Bit (MSB) sub-Digital-to-Analog Converter (subDAC). In addition, it utilizes scaling capacitors to execute a fold-and-shrink technique for the Least Significant Bit (LSB) subDAC, thereby yielding the combined output of the DAC. A 12-bit SAR ADC prototype has been developed using a 90 nm CMOS process. It occupies an area of 0.029 mm<sup>2</sup> and is designed for Cochlear Implant applications. Operating at 1 V with a sampling rate of 1 MS/s, this ADC demonstrates an effective number of bits (ENOB) of 11.5, a signal-to-noise-and-distortion ratio (SNDR) of 71.22 dB, a bandwidth of 8.05 kHz, and a power consumption of 0.85 μW. Both MSB and LSB subDACs are configured as 6-bit with a 16-fold scaling capacitor for LSB voltage shrinkage. A newly developed low-power dynamic comparator (CMP) augmented by placing a capacitor at the output of MSB subDAC is utilized to minimize kick-back noise, which highlights the design's focus on both power efficiency and noise suppression.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"166 ","pages":"Article 106885"},"PeriodicalIF":1.9,"publicationDate":"2025-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145050206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0