Microelectronics Journal最新文献_第3页

Asymmetric Trench SiC MOSFET With Integrated Channel Accumulation Diode for Enhanced Reverse Conduction and Switching Characteristics 集成沟道累积二极管的非对称沟道碳化硅 MOSFET，可增强反向传导和开关特性

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-10-09 DOI: 10.1016/j.mejo.2024.106436

Sheng Gao , Xianfeng Zhang , Qi Wang , Shengqi Yu , Yang Zuo , Hongsheng Zhang , Yi Huang

{"title":"Asymmetric Trench SiC MOSFET With Integrated Channel Accumulation Diode for Enhanced Reverse Conduction and Switching Characteristics","authors":"Sheng Gao , Xianfeng Zhang , Qi Wang , Shengqi Yu , Yang Zuo , Hongsheng Zhang , Yi Huang","doi":"10.1016/j.mejo.2024.106436","DOIUrl":"10.1016/j.mejo.2024.106436","url":null,"abstract":"<div><div>A novel asymmetric trench Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor (SiC MOSFET), featuring an integrated channel accumulation diode (CAD-MOS), has been proposed and investigated through numerical simulation. This innovative design aims to mitigate switching losses and eliminate the bipolar degradation of the body diode. The current spreading layer (CSL) channel, strategically positioned in the centre of the dummy gate, offers a low-barrier reverse conduction path. This represents a substantial advancement over the traditional PN body diode, significantly reducing the reverse conduction voltage drop from 2.84 V in the PN body diode to a mere 1.39 V in the CAD-MOS. Meanwhile, the reverse recovery charge of the CAD-MOS is reduced to 0.95 μC/cm<sup>2</sup>, and the peak reverse recovery current stands at 45 A/cm<sup>2</sup>. Compared to conventional asymmetrical trench SiC MOSFET (CON-MOS), the CAD-MOS exhibits a 68.1% reduction in reverse recovery charge and a 63.4% decrease in peak reverse recovery current. The split-gate design also reduces the device gate to source capacitance (<em>C</em><sub>GS</sub>), resulting in a 17.4% reduction in total switching losses to 3.64 mJ/cm<sup>2</sup>. CAD-MOS also exhibits a reduced gate turn-on charge and demonstrates an enhancement in high-frequency figure of merit (HF-FOM) by 8.1%.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142415883","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Scalable, low-power and high-performance active-RC complex band-pass/low-pass filter with automatic frequency tuning applied to the Internet of Things 应用于物联网的可扩展、低功耗、高性能有源 RC 复杂带通/低通滤波器，具有自动频率调谐功能

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-10-09 DOI: 10.1016/j.mejo.2024.106430

Shengping Yuan, Huizhe Xuan, Haigang Feng, Xian Tang

{"title":"Scalable, low-power and high-performance active-RC complex band-pass/low-pass filter with automatic frequency tuning applied to the Internet of Things","authors":"Shengping Yuan, Huizhe Xuan, Haigang Feng, Xian Tang","doi":"10.1016/j.mejo.2024.106430","DOIUrl":"10.1016/j.mejo.2024.106430","url":null,"abstract":"<div><div>This article introduces a comprehensive 3rd Chebyshev active-RC complex band-pass/low-pass filter with an automatic cut-off frequency tuning circuit. The designed filter achieves 2 dB step gain control within the range of −6 dB–24 dB and 4 different bandwidth modes including low-pass modes and complex band-pass modes. A compact fully-differential (FD) amplifier with feedforward compensation and reverse pole splitting technique is used to meet the stringent filter's performance. The novel amplifier achieves an open loop gain of 62 dB and a maximum unity-gain bandwidth (UGB) of 732 MHz with VDD = 0.9 V and 0.32 mW of power dissipation. Using the proposed amplifier, the filter achieves the lowest power consumption reported in the literature for active-RC implementations and 30 % power reduction over similar active-RC filters. By employing an optimized solution for dynamic allocation of inter-stage gain, the filter achieves a maximum in-band-IIP3 of +25.7 dBm and an improvement of 2 dB. Also, an automatic frequency tuning scheme is used to eliminate the effect of process variation. The filter is fabricated in 22 nm CMOS process occupying 0.44 mm <span><math><mrow><mo>×</mo></mrow></math></span> 0.44 mm area and consuming 1.8 mW and 1.2 mW from 0.9 V supply voltage in Wi-Fi and BLE modes, respectively. The maximum figure of merit (FoM) is 142.6 dB/J. The RC tuning circuit has a precision of 1.5 % and covers a range of 20 %.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142445689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Anti-machine-learning-attack strong PUF design based on multi-path delay selection strategy 基于多路径延迟选择策略的抗机器学习攻击强 PUF 设计

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-10-09 DOI: 10.1016/j.mejo.2024.106434

Gang Li , Xilong Shao , Pengjun Wang , Xuejiao Ma , Hui Li , Hao Ye

{"title":"Anti-machine-learning-attack strong PUF design based on multi-path delay selection strategy","authors":"Gang Li , Xilong Shao , Pengjun Wang , Xuejiao Ma , Hui Li , Hao Ye","doi":"10.1016/j.mejo.2024.106434","DOIUrl":"10.1016/j.mejo.2024.106434","url":null,"abstract":"<div><div>Physical unclonable functions (PUF) have significant potential for application in information security. However, strong PUFs are vulnerable to machine learning (ML) modeling attacks, which severely limit their application in device authentication. Despite a variety of resistance techniques, strong PUFs suffer from hardware cost and stability deficiencies. This study proposes an anti-machine-learning-attack strong PUF based on a multi-path delay selection strategy through research on the entropy source of a strong PUF and the delay signal selection mechanism. First, we constructed a deviation source circuit based on multiplexers to increase the diversity of the delay signal transmission paths. Second, we constructed a delay selection circuit based on the logic gates. This circuit dynamically selects the delay signals with the same transmission path in the deviation source using AND and OR gates. Subsequently, the deviation source and delay selection circuits were utilized to construct the delay module, and the interconnection module was inserted between the delay modules to achieve alternating appearances of different types of logic gates along the delay path. Finally, RS flip-flops were employed to make decisions on the bias signals with the same delay path, and the final response was output through an XOR operation. The proposed PUF was implemented on a Xilinx Artix-7 FPGA, and the prediction accuracy of the four typical ML models was below 59 % (with 500,000 challenge-response pairs as the training set). Moreover, the proposed PUF structure is scalable and exhibits better performance in terms of hardware cost and stability than existing classic structures.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142433162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 68.5 dB-SNDR, 12.4-fJ/conv.-step, 100-MS/s pipelined-SAR ADC with PVT-enhanced circuitry 具有 PVT 增强电路的 68.5 dB-SNDR、12.4-fJ/conv.-step、100-MS/s pipelined-SAR ADC

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-10-08 DOI: 10.1016/j.mejo.2024.106432

Haolin Han, Ruili Ren, Yi Shen, Ruixue Ding, Shubin Liu, Hongzhi Liang

{"title":"A 68.5 dB-SNDR, 12.4-fJ/conv.-step, 100-MS/s pipelined-SAR ADC with PVT-enhanced circuitry","authors":"Haolin Han, Ruili Ren, Yi Shen, Ruixue Ding, Shubin Liu, Hongzhi Liang","doi":"10.1016/j.mejo.2024.106432","DOIUrl":"10.1016/j.mejo.2024.106432","url":null,"abstract":"<div><div>This paper presents a signal-chain friendly 12-bit pipelined-successive approximation register (SAR) analog-to-digital converter (ADC) in 40nm CMOS, which is optimized to achieve a 68.5 dB-SNDR, 100-MS/s sample rate with 54.5<span><math><mtext>%</mtext></math></span> of maximum available input range. The implemented ADC employs an improved clock booster and latch-register to achieve high on-conductance of nmos switches and low-leakage data storage. It also explores an adaptive non-overlapping complementary clock generator and a dedicated <span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>C</mi><mi>M</mi></mrow></msub></math></span> buffer to accommodate process, voltage, and temperature (PVT) conditions. The relative variation of non-overlapping time is reduced by 50<span><math><mtext>%</mtext></math></span> compared to the conventional method, and the signal-to-distortion ratio (SDR) of residue amplification is improved by 8dB . Moreover, on-chip bit weight calibration is implemented to address the gain error brought by capacitor mismatch and inner-stage gain error. The prototype ADC is simulated under 5 corners, −40 to 125  <span><math><mo>±</mo></math></span> 2.5<span><math><mtext>%</mtext></math></span>. For a Nyquist input, the simulated SNDR under typical corner is 68.5dB , which can remain over 66dB under PVT conditions. The achieved Walden Figure of Merit (FoM) is 12.4-fJ/conv.-step.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-10-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142433163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Preventing short violations in clock routing with an SVM classifier before powerplanning and placement 在电源规划和布局前使用 SVM 分类器防止时钟布线中的短路现象

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-10-05 DOI: 10.1016/j.mejo.2024.106429

Qi Liu , Ming Ling , Yanxiang Zhu , Yibo Rui , Rui Wang

引用次数: 0

A 2–36 GHz CMOS LNA with π-Network-Based wideband interstage matching technique for software-defined radio systems 用于软件定义无线电系统的 2-36 GHz CMOS LNA，采用基于 π 网络的宽带级间匹配技术

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-10-03 DOI: 10.1016/j.mejo.2024.106431

Hanqi Gao, Chao Yang, Jing Jin, Jianjun Zhou

{"title":"A 2–36 GHz CMOS LNA with π-Network-Based wideband interstage matching technique for software-defined radio systems","authors":"Hanqi Gao, Chao Yang, Jing Jin, Jianjun Zhou","doi":"10.1016/j.mejo.2024.106431","DOIUrl":"10.1016/j.mejo.2024.106431","url":null,"abstract":"<div><div>With the advance in wireless communication, next-generation software-defined radio (SDR) systems require transceivers to operate in both sub-6GHz and millimeter-wave (mmWave) band and support multiple standards. However, bridging sub-6GHz frequencies with millimeter-wave bands exceeding 30 GHz remains a challenge for conventional wideband LNAs. To surmount this, a 2–36 GHz CMOS low-noise amplifier (LNA) designed for SDR systems is introduced in this paper. An innovative wideband input matching network capable of spanning both frequency domains is proposed. The methodology effectively mitigates the impact of vast parasitic capacitances, achieving wideband input matching against Electrostatic Discharge (ESD) and on-chip decoupling capacitor parasitic. In addition, a π-network-based wideband interstage matching technique is adopted to extend bandwidth of gain. A tri-stage prototype of the proposed LNA, designed using a 40-nm CMOS process, is designed to validate our design strategies. The post-simulation outcomes reveal a peak gain of 14 dB with a -3dB bandwidth ranging from 2 to 36 GHz, equating to a fractional bandwidth of 178 %. The Noise Figure (NF) is commendably uniform across the frequency spectrum, stabilizing at 5 dB. Furthermore, the third-order input intercept point (IIP3) is −4.2dBm to -3dBm across the bandwidth. The performance is achieved with a power of 19.4 mW and within a core area of 0.1 mm<sup>2</sup>.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-10-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142415882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A V-band injection locking tripler with 26.8% locking range and 7.3-dBm output power in 65 nm CMOS 采用 65 纳米 CMOS 的 V 波段注入锁定三分频器，锁定范围达 26.8%，输出功率为 7.3 dBm

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-09-30 DOI: 10.1016/j.mejo.2024.106426

Yue Liang , Qin Chen , Jing Feng , Lin Lu , Tao Zhang , Xiangning Fan , Lianming Li

引用次数: 0

An 11-bit low power column-parallel single slope ADC with comparator toggle prediction technique for CMOS image sensor 采用比较器切换预测技术的 11 位低功耗列并行单斜率 ADC，适用于 CMOS 图像传感器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-09-28 DOI: 10.1016/j.mejo.2024.106427

Xiaolin Shi , Shaomeng Li , Kaiming Nie

引用次数: 0

Fault-tolerant routing for reliable packet transmission in on-chip networks 芯片网络中可靠数据包传输的容错路由选择

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-09-28 DOI: 10.1016/j.mejo.2024.106425

Yiming Ouyang , Tianbao Zhang , Jianhua Li , Huaguo Liang

{"title":"Fault-tolerant routing for reliable packet transmission in on-chip networks","authors":"Yiming Ouyang , Tianbao Zhang , Jianhua Li , Huaguo Liang","doi":"10.1016/j.mejo.2024.106425","DOIUrl":"10.1016/j.mejo.2024.106425","url":null,"abstract":"<div><div>In deep submicron technology, integrated circuits are susceptible to various factors, leading to increased probabilities of chip failures. The routers within NoC, connecting processor cores, also experience elevated fault rates, thereby impacting normal communication between processors. Therefore, implementing fault-tolerant mechanisms in on-chip networks becomes particularly crucial. In this paper, we propose a fault-tolerant routing scheme to ensure the accurate transmission, injection, and ejection of packets, even in the event of router failures at any node in the NoC. We have enhanced the router architecture by integrating bypass controllers (BCs) to connect east–west and north–south links, and linking these BCs to the local. This modification enables uninterrupted communication between cores. Based on this architecture, we propose a straightforward routing algorithm aimed at minimizing detours and ensuring packet transmission along the shortest path , thus reducing transmission latency. Experimental results demonstrate that our proposed fault-tolerant scheme significantly enhances reliability under scenarios involving multiple faulty routers when compared to existing schemes.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142415878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design of radiation hardened latch with low delay and tolerance of quadruple-node-upset in 32 nm process 在 32 纳米工艺中设计具有低延迟和四节点上移容差的辐射加固锁存器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2024-09-27 DOI: 10.1016/j.mejo.2024.106428

Zhengfeng Huang , Xin Chen , Xinyu Jiang , Lei Ai , Huaguo Liang , Yiming Ouyang , Tianming Ni

{"title":"Design of radiation hardened latch with low delay and tolerance of quadruple-node-upset in 32 nm process","authors":"Zhengfeng Huang , Xin Chen , Xinyu Jiang , Lei Ai , Huaguo Liang , Yiming Ouyang , Tianming Ni","doi":"10.1016/j.mejo.2024.106428","DOIUrl":"10.1016/j.mejo.2024.106428","url":null,"abstract":"<div><div>As integrated circuit technology continues to shrink, single-event multiple-node-upset induced by charge sharing effect has become an important factor affecting chip reliability. This paper proposes two quadruple-node-upset hardened latches: 4DICE-C and 4DICE-V. These two latches are both based on dual-interlocked-storage-cell (DICE) that can achieve single-node-upset self-recovery. Besides, a quadruple-modular redundancy fault-tolerant mechanism is constructed. The 4DICE-C uses the clocked quadruple-input C-element at the output stage, the 4DICE-V uses clocked voter at the output stage. Compared with previous hardened latches containing C-elements, the 4DICE-V is less sensitive to high impedance state and can efficiently tolerate soft errors at internal nodes. In addition, compared with previous single-event triple-node-upset and quadruple-node-upset hardened latches, the 4DICE-C latch has achieved 100 % tolerance efficiency of single-event quadruple-node-upset, the best delay overhead and APDP comprehensive overhead, 18.69 % lower than average delay.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":null,"pages":null},"PeriodicalIF":1.9,"publicationDate":"2024-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142415879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0