{"title":"A 28 nm Ising machine with adaptive majority voter and reduction algorithms for high-performance combinatorial optimization","authors":"Jingyang Chen , Zhiping Yu , Xiaolei Zhu","doi":"10.1016/j.mejo.2025.106621","DOIUrl":"10.1016/j.mejo.2025.106621","url":null,"abstract":"<div><div>The Ising model has shown outstanding potential for solving combinatorial optimization problems, but conventional processors based on the von Neumann architecture have difficulty emulating the behavior of spins in parallel. Therefore, to tackle combinatorial optimization problems efficiently, specialized processors with Ising models are required. In this work, an approximate logistic complementary spin update (ALCU) model is proposed that enhances the accuracy of the solution by 3.34% compared to the previous approximation methodology. In addition, an adaptive analog majority voter (AMV) is proposed, which can support higher interaction coefficient bit-width and more interaction spins with lower hardware overhead. Then, the Ising machine with 100 interaction spins in King’s Graph topology is implemented based on a 28 nm CMOS process. More than 67% less hardware overhead is required when compared to Ising machines based on digital adders. The coefficient precision is increased to 2.3x, and the number of interaction spins is increased to 1.6x compared to the Ising machine based on prior AMV.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106621"},"PeriodicalIF":1.9,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143619231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jen-Chieh Liu , Jian-Sheng Li , Yan-Xun Chen , Yu-Lung Lo
{"title":"A VRO-based TDC with a constant timing resolution ratio between coarse-tuning and fine-tuning stages for a light sensor application","authors":"Jen-Chieh Liu , Jian-Sheng Li , Yan-Xun Chen , Yu-Lung Lo","doi":"10.1016/j.mejo.2025.106637","DOIUrl":"10.1016/j.mejo.2025.106637","url":null,"abstract":"<div><div>This study designs a vernier ring oscillator (VRO)-based time-to-digital converter (TDC), ensuring a proportional relationship between the timing resolutions of the coarse-tuning stage (CTS) and fine-tuning stage (FTS) under process, voltage, and temperature (PVT) variations. The design allows flexibility in extending the bit number to a wide input range during CTS. The timing resolutions of CTS and FTS were defined by the rise and fall times. Therefore, the timing ratio between CTS and FTS of VRO-based TDC remained constant under the PVT variations. This 14-bit TDC was fabricated using a 0.18 μm standard CMOS process with a core area of 45 μm × 200 μm. The measured timing resolution of the proposed VRO-based TDC was 125 ps, and the input range was from 10 to 200 ns. The DNL and INL values were less than ±0.244 and ± 0.336 LSB, respectively. The proposed VRO-based TDC was also integrated with a light sensor for Internet of Things applications.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106637"},"PeriodicalIF":1.9,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143592900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Enhanced performance of p-GaN HEMT via partial etched AlGaN","authors":"Qingxin Liu , Shuang Wu , Kailin Ren , Luqiao Yin , Jianhua Zhang","doi":"10.1016/j.mejo.2025.106627","DOIUrl":"10.1016/j.mejo.2025.106627","url":null,"abstract":"<div><div>P-GaN high electron mobility transistor (HEMT) is currently the most commonly used enhanced GaN HEMT device. However, due to the presence of defects and traps, as well as the strong self-heating effect, p-GaN HEMT faces challenges with low breakdown voltage and poor device stability. In this study, a p-GaN HEMT structure via partially etched AlGaN has been proposed. The electrical and thermal performances of this device are thoroughly characterized and compared with conventional p-GaN HEMT. Through the proposed device structure, the breakdown voltage is increased from 290 V to 480 V, representing a 65 % improvement compared to conventional HEMT fabricated on the same wafer. The self-heating effect is also suppressed, resulting in a temperature reduction of 41.76 °C at a power level of 3.48 W. And more distinct temperature contrast images are obtained through thermoreflectance thermal imaging technology. This study provides a potential solution for fully leveraging the performance of p-GaN HEMT devices.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106627"},"PeriodicalIF":1.9,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143577538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"S-ANN: Synchronous TCAD device simulation of FinFET using Artificial Neural Network","authors":"Yansen Liu , Xiaonian Liu , Ying Zhou , Peng Cao","doi":"10.1016/j.mejo.2025.106630","DOIUrl":"10.1016/j.mejo.2025.106630","url":null,"abstract":"<div><div>The Fin Field-Effect Transistor (FinFET) plays a crucial role in integrated circuits due to its superior control capabilities and low leakage current. However, its complex structure often leads to substantial computational demands and significant time consumption during Technology Computer-Aided Design (TCAD) simulations. To address these challenges, we innovatively propose a synchronous TCAD device simulation model based on Artificial Neural Network (ANN) for FinFET at advanced technology nodes, abbreviated as S-ANN. This model systematically extracts FinFET characteristics under various physical sizes and bias conditions from TCAD simulations and further analyzes transient response data contained in TDR files to build a training dataset, thereby enabling effective training of the S-ANN model. Through rigorous testing and evaluation, S-ANN has demonstrated high compatibility with Sentaurus TCAD and the capability to accurately simulate TCAD electrical characteristics. In addition, Nanosheet FET was used to verified the generalization capability of the S-ANN model. Compared to traditional TCAD simulations, the S-ANN model significantly reduces both computational resource usage and simulation time, while effectively overcoming convergence problems. This advancement offers strong support for the rapid design and optimization of advanced semiconductor devices.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106630"},"PeriodicalIF":1.9,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143577945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xin Wang , Qingsong Zhao , Fanyi Meng , Keping Wang
{"title":"A multi-module parallel current-sharing circuit and control strategy for brick power supplies","authors":"Xin Wang , Qingsong Zhao , Fanyi Meng , Keping Wang","doi":"10.1016/j.mejo.2025.106629","DOIUrl":"10.1016/j.mejo.2025.106629","url":null,"abstract":"<div><div>To address the issue of unbalanced output currents in multi-module parallel power applications, this paper proposes a novel parallel current-sharing circuit structure and control strategy, which is suitable for the standard packaging of brick power supplies. This approach eliminates the need for additional controllers and current-sharing circuits and can enhance system stability and reliability. Furthermore, this paper introduces a design method for multi-order RC low-pass filters in series, effectively reducing voltage ripple and improving ADC sampling accuracy. To validate the proposed theory, a simulation model was developed using two 2 kW full-brick power converters. The results demonstrate that the proposed method significantly improves current-sharing accuracy compared to systems without a current-sharing control strategy.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106629"},"PeriodicalIF":1.9,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143610334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of a low power LED driver with adjustable LDO","authors":"Binjie Shi , Zhenglin Li , Hao Fang , Jiadong Li","doi":"10.1016/j.mejo.2025.106622","DOIUrl":"10.1016/j.mejo.2025.106622","url":null,"abstract":"<div><div>The issue of high power consumption in the standby state of the driver chip for conventional LED is addressed by proposing an adjustable LDO. This LDO optimizes the static power consumption current of the LED driver chip through a power management circuit. In standby mode, a portion of the LDO circuit and the driver chip display circuit are deactivated, effectively reducing the static power consumption current of the driver chip. The standby mode static power consumption current of the LED driver chip equipped with adjustable LDO is measured to be 46.82μA, while the static power consumption current of the LED driver chip without adjustable LDO amounts to 151.83μA. In standby mode, compared to the non-adjustable option, there is a reduction of 105μA in adjustable power consumption current, with a corresponding static power consumption of only 0.23 mW for the LED driver chip. The LED driver chip designed in this paper is realized using a 180 nm BCD process.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106622"},"PeriodicalIF":1.9,"publicationDate":"2025-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143562044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new power-rail clamp circuit for on-chip electrostatic discharge protection","authors":"Yaping Yue , Shi Pu , Ruizhen Wu , Ronghui Hou","doi":"10.1016/j.mejo.2025.106617","DOIUrl":"10.1016/j.mejo.2025.106617","url":null,"abstract":"<div><div>Power-rail clamp circuit is crucial for the whole-chip electrostatic discharge (ESD) protection. In this paper, a new power-rail clamp circuit for on-chip ESD protection is proposed and verified by silicon. A dedicated false-triggering suppression circuit is introduced to make sure that the proposed clamp circuit keeps off during fast power-up events. By skillfully incorporating slew rate and voltage detection mechanisms are, offering a low clamp voltage and a reliable turn-off functionality. Experimental results from fabricated silicon die verify that the proposed clamp circuit exhibits high immunity to false triggering, making it suitable for robust ESD protection. Comparisons with the traditional solution are also presented.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106617"},"PeriodicalIF":1.9,"publicationDate":"2025-03-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143549258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Qiang Zhou , Sirui Peng , Taoran Shen , Jie Yin , Tieli Sun , Xiaoyong Xue
{"title":"Garbage collection optimization with data separation for large data storage in deep learning applications","authors":"Qiang Zhou , Sirui Peng , Taoran Shen , Jie Yin , Tieli Sun , Xiaoyong Xue","doi":"10.1016/j.mejo.2025.106620","DOIUrl":"10.1016/j.mejo.2025.106620","url":null,"abstract":"<div><div>Deep learning has revolutionized numerous domains, creating an urgent need for storage systems capable of handling massive datasets and the intensive computational demands inherent to these workloads. Solid-State Drives (SSDs), known for their fast random access, low power consumption, and shock resistance, have emerged as a preferred storage medium in this context. However, traditional SSDs face critical challenges, including garbage collection (GC) overhead, write amplification, and inefficiencies in the software storage stack, stemming from the intrinsic characteristics of NAND flash and limitations in the existing storage ecosystem. These challenges underscore the necessity for specialized SSD controller chip designs tailored for deep learning workloads, addressing performance bottlenecks and optimizing data management to meet the unique demands of AI-driven applications. In this work, we implemented an open-channel SSD (OCSSD) based on a Xilinx FPGA, which can effectively alleviate the above-mentioned issues by exposing the structural characteristics of NAND flash to the host. To mitigate the performance cliff of I/O requests during GC operations, the link distance for data transmission is shortened by decoupling the host end and the device end. Moreover, the valid data migration and the GC operation frequency are both dramatically reduced by detecting and separating hot data and cold data to improve the overall performance of the SSD system. To verify the superiority of our design, we build a test platform through hardware and software co-design. The experimental results show that random read and random write bandwidth are increased by 159.7 % and 25.3 % compared to the mainstream SSDs, respectively. The latency of a single GC operation is reduced by an average of 12.64 % and the GC frequency is lowered by up to 64.8 %.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106620"},"PeriodicalIF":1.9,"publicationDate":"2025-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143549259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A high speed adaptive reflection cancellation equalization circuit with Floating Tap FFE and Loop-Refactored DFE for ADC-DSP-based wireline receiver","authors":"Cewen Liu , Xingyun Qi , Fangxu Lv, Qiang Wang, Liquan Xiao, Xiaoyue Hu, Chaolong Xu, Zhouhao Yang, Meng Li, Mingche Lai","doi":"10.1016/j.mejo.2025.106612","DOIUrl":"10.1016/j.mejo.2025.106612","url":null,"abstract":"<div><div>High speed communication networks depend on higher data rates for bandwidth expansion, but face challenges in maintaining signal integrity when data rates exceed 100 Gb/s due to ISI and reflection, which hinder transmission speed advancements. This paper proposes the design of an adaptive reflection cancellation circuit for high-speed 4-level pulse amplitude (PAM4) serializer-deserializer (Serdes) receiver based on analog-to-digital converter (ADC) + digital signal processing (DSP) architecture. The proposed parallel Floating Tap Feedforward equalization(FT-FFE) effectively mitigates the impact of reflection without the need for a large number of equalizers, thereby reducing power consumption overhead. A Loop-Refactored decision feedback equalizer (LR-DFE) is implemented to mitigate timing constraints in ADC-DSP based high-speed wireline receivers, improving system performance and timing reliability. The tap coefficients are adaptively updated in combination with the Least Mean Square (LMS) algorithm. Simulation and FPGA platform validation results demonstrate that at a data rate of 56 Gb/s, the bit error rate(BER) is below 1e-12 through a channel with 39 dB insertion loss(IL).</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106612"},"PeriodicalIF":1.9,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143562046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Parasitic-induced multi-zero generation and port-fusion compact filter based on 3-D through-silicon via technology","authors":"Xiangkun Yin, Xiangyu Ma, Nairong Liu, Libo Qian, Tao Zhang, Qijun Lu, Zhangming Zhu","doi":"10.1016/j.mejo.2025.106618","DOIUrl":"10.1016/j.mejo.2025.106618","url":null,"abstract":"<div><div>A approach to achieving compactness and performance enhancement in lowpass filter (LPF) is described in this work. By leveraging the parasitic inductance of metal interconnects as inductive components, the proposed approach significantly reduces the overall size of the filter. Additionally, the combined effect of parasitic inductance and source-load coupling parasitic capacitance is utilized to create multiple transmission zeros, leading to improved isolation and wider bandwidth. Furthermore, a port fusion technique is introduced, which reduces the number of ports, minimizing interconnect losses and further enhancing compactness. The proposed LPF occupies a compact space of 0.31 × 0.34 mm<sup>2</sup>, features a cut-off frequency of 6.31 GHz, achieves an insertion loss of 30 dB at 30 GHz, and maintains a return loss below 0.4 dB.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106618"},"PeriodicalIF":1.9,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143520968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}