Microelectronics Journal最新文献_第4页

A simulation study of SiC trench JFET with embedded diode for performance improvement 为提高碳化硅沟槽场效应管的性能，对其进行了仿真研究

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-07-02 DOI: 10.1016/j.mejo.2025.106793

Shida Zhang , Xintian Zhou , Yun Tang , Yunpeng Jia , Dongqing Hu , Yu Wu , Yuanfu Zhao

{"title":"A simulation study of SiC trench JFET with embedded diode for performance improvement","authors":"Shida Zhang , Xintian Zhou , Yun Tang , Yunpeng Jia , Dongqing Hu , Yu Wu , Yuanfu Zhao","doi":"10.1016/j.mejo.2025.106793","DOIUrl":"10.1016/j.mejo.2025.106793","url":null,"abstract":"<div><div>This paper proposes and studies two novel structures of SiC trench JFET (TJFET) using TCAD simulation tool. One is integrated with PN junction diode (PN-TJFET), and the other is integrated with Schottky barrier diode (SBD-TJFET). For conventional TJFET (C-TJFET), the addition of PN junction and Schottky barrier diodes are used to improve the performance of the device in the 3rd quadrant. It is shown that the reverse turn-on voltage could be reduced from −8.5 V to −2.1 V in the PN-TJFET, while to −0.9 V in the SBD-TJFET, thus significantly lowering the power loss when working for freewheeling. Moreover, both the PN-TJFET and SBD-TJFET demonstrate excellent characteristics in the 1st quadrant. The Miller capacitance <em>C</em><sub>GD</sub> and gate-to-drain charge <em>Q</em><sub>GD</sub> are nearly halved as compared to the C-TJFET, leading to a reduction in switching loss of nearly 56 %. These results, combined with their good process feasibility, indicate that the proposed structures have great potential for applications in the high-frequency domain.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"164 ","pages":"Article 106793"},"PeriodicalIF":1.9,"publicationDate":"2025-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144548710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Research on radiation hardening of oscillator circuits based on LDMOS devices 基于LDMOS器件的振荡电路辐射硬化研究

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-06-30 DOI: 10.1016/j.mejo.2025.106780

Xiaohui Li , Ming Qiao , Jitao Li , Zhaoji Li , Qiang Wang , Hongjun Wang , Bo Zhang

{"title":"Research on radiation hardening of oscillator circuits based on LDMOS devices","authors":"Xiaohui Li , Ming Qiao , Jitao Li , Zhaoji Li , Qiang Wang , Hongjun Wang , Bo Zhang","doi":"10.1016/j.mejo.2025.106780","DOIUrl":"10.1016/j.mejo.2025.106780","url":null,"abstract":"<div><div>The current radiation-hardened oscillator circuit commonly employs CMOS devices, which exhibit excellent resistance to total-ionizing-dose (TID) effects, but have poor immunity to single-event effects (SEEs). In contrast to CMOS devices, LDMOS devices feature slower carrier mobility, a thicker oxide layer, higher breakdown voltage, larger process feature size, and radiation-insensitive parasitic parameters, thereby demonstrating potential for SEEs mitigation. Leveraging these advantages, this work presents a novel LDMOS-based oscillator circuit design that integrates single-event filtering techniques to eliminate interference from high-LET particles (up to 75 MeV cm<sup>2</sup>/mg). The designed TID-hardened oscillator circuit operates normally under a TID radiation level of 200 Krad(Si). This circuit exhibits no functional anomalies during single-event effect testing, with a frequency shift rate of only 0.016 % and a duty cycle variation rate of 0.01 %. Under TID radiation, the output frequency shift rate is merely 4.5 Hz/krad(Si), and the duty cycle variation rate is 0.175 %/Krad(Si).</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"164 ","pages":"Article 106780"},"PeriodicalIF":1.9,"publicationDate":"2025-06-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144522454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 65.7-dB SNDR 2-MHz bandwidth low-power bandpass DSM based on passive N-path filters with enhanced out-of-band rejection 基于增强带外抑制的无源n路滤波器的65.7 db SNDR 2-MHz带宽低功率带通DSM

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-06-27 DOI: 10.1016/j.mejo.2025.106779

Lijuan Yi , Wenxin He , Xian Tang , Yang Zhang , Kong-Pang Pun

{"title":"A 65.7-dB SNDR 2-MHz bandwidth low-power bandpass DSM based on passive N-path filters with enhanced out-of-band rejection","authors":"Lijuan Yi , Wenxin He , Xian Tang , Yang Zhang , Kong-Pang Pun","doi":"10.1016/j.mejo.2025.106779","DOIUrl":"10.1016/j.mejo.2025.106779","url":null,"abstract":"<div><div>This paper introduces a low-power 6th-order single-loop N-path filter based bandpass delta-sigma modulator (NP-BP DSM). By leveraging the high-Q bandpass response of the N-path filter, the proposed 6th-order NP-BP DSM achieves an enhanced signal transfer function (STF) with superior out-of-band rejection, thereby alleviating the requirements for channel selection filters in wireless communication systems. A generalized design methodology for the high-order NP-BP DSMs is presented, which includes deriving and systematically organizing 2nd-to-(2L) <sup>th</sup>-order noise transfer function (NTF) expressions, analyzing system models of NP-BP DSMs from 2nd to 6th-order and comparing lowpass LTFs with bandpass LTFs to provide general guidelines for designing component parameters. This work further investigates the impact of excess loop delay (ELD) and proposes a compensation strategy to address it. As a proof of concept, a 6th-order non-time-interleaved modulator fabricated in 65-nm CMOS achieves 2-MHz signal bandwidth with 100–167 MHz tunable intermediate frequency (IF). Measured results demonstrates a peak SNDR of 65.7 dB without any calibration while consuming only 342 μW from 1-V power supply, achieving a Scheier Figure of Merit (FoM) of 163.4 dB.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"164 ","pages":"Article 106779"},"PeriodicalIF":1.9,"publicationDate":"2025-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144557043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Development of a 65V low Ron,sp N-type LDMOS on 180 nm BCD platform 180nm BCD平台上65V低Ron，sp n型LDMOS的研制

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-06-26 DOI: 10.1016/j.mejo.2025.106778

Qi Ding , Ning Ning , Jun Huang , Renxiong Li , Yu Wang , Yutuo Guo , Kunqin He , Yaxin Liu , Ziyi Zeng , Huaishan Wang , Juan Tang , Qiuyue Huo , Lulu Peng , Zhaoji Li , Bo Zhang , Ming Qiao

{"title":"Development of a 65V low Ron,sp N-type LDMOS on 180 nm BCD platform","authors":"Qi Ding , Ning Ning , Jun Huang , Renxiong Li , Yu Wang , Yutuo Guo , Kunqin He , Yaxin Liu , Ziyi Zeng , Huaishan Wang , Juan Tang , Qiuyue Huo , Lulu Peng , Zhaoji Li , Bo Zhang , Ming Qiao","doi":"10.1016/j.mejo.2025.106778","DOIUrl":"10.1016/j.mejo.2025.106778","url":null,"abstract":"<div><div>In this article, a 65V low specific on-resistance (R<sub>on,sp</sub>) N type laterally diffused metal oxide semiconductor (LDMOS) is proposed. It is developed basing on 180 nm BCD platform. The device uses high voltage N type well (HVNW) as the main voltage sustaining layer, deep N-type well (DNW) helps sustain the high voltage between drift region and substrate and also isolates the bulk of the device from the substrate. Because of no using of N type buried (BN) layer, the epitaxial layer is no need to become thicker compared with 8–40V LDMOS. The optimization of breakdown voltage (BV) and R<sub>on,sp</sub> is conducted through high voltage N type well (HVNW) implantation dose and structure parameters adjustment: With implantation dose increasing, BV increases and then decreases quickly; With length of LOCOS (Ls) increasing, BV increases; And under different drift region concentration, length of overlap (Lo) and length of interface (Li) has different impact on BV. Finally, the competitive performance is achieved that R<sub>on,sp</sub> of 65V N type LDMOS (NLDMOS) is 85 mΩ mm<sup>2</sup> when BV is 92V. According to physical mechanism and TCAD simulation, also combining the experiments results, the model is proposed that Li is the critical structure parameter for this NLDMOS under relatively high HVNW dose because of the impact ionization occurring space at Li area. Shorter Li helps to weaken the impact ionization and is beneficial to depletion region extending and BV increasing. Finally, the DC electrical characteristic curves and parameters are measured which demonstrate that the optimization of 65V NLDMOS does not lead the leakage degrading.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"164 ","pages":"Article 106778"},"PeriodicalIF":1.9,"publicationDate":"2025-06-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144572158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 5.9-to-6.9 GHz digital sub-sampling PLL with static phase error control technology achieving 178fs RMS integrated jitter 5.9 ~ 6.9 GHz数字分采样锁相环，采用静态相位误差控制技术，实现178fs RMS集成抖动

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-06-25 DOI: 10.1016/j.mejo.2025.106777

Xueming Wei, Jiami Tang, Linzheng Lu, Leitong Xie

引用次数: 0

A 14-GS/s 8-bit time-interleaved SAR ADC with multi-path bootstrapped switch and low-jitter sampling PLL in 28-nm CMOS 基于28纳米CMOS的14-GS/s 8位时间交错SAR ADC，具有多径自举开关和低抖动采样锁相环

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-06-21 DOI: 10.1016/j.mejo.2025.106770

Jiawei Ding , Xuan Guo , Shan Lu , Qing Su , Tao liu , Hanbo Jia , Yihan Li , Xinyu Liu

引用次数: 0

Up To 99.6 % duty cycle digital PWM using 180-nm CMOS process 高达99.6%的占空比数字PWM采用180纳米CMOS工艺

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-06-21 DOI: 10.1016/j.mejo.2025.106768

Chua-Chin Wang , Oliver Lexter July Alvarez Jose , Venkata Naveen Kolakaluri

{"title":"Up To 99.6 % duty cycle digital PWM using 180-nm CMOS process","authors":"Chua-Chin Wang , Oliver Lexter July Alvarez Jose , Venkata Naveen Kolakaluri","doi":"10.1016/j.mejo.2025.106768","DOIUrl":"10.1016/j.mejo.2025.106768","url":null,"abstract":"<div><div>Prior digital pulse width modulation (DPWM) techniques are implemented with numerous D flip-flops (DFFs), which exponentially increase with the resolution and can easily affected by clock skew. This study presents a high-resolution (N = 8) DPWM design that uses a small number of DFFs (The prior architectures used the 2<span><math><msup><mrow></mrow><mrow><mi>N</mi></mrow></msup></math></span> number of DFFs in their design, while in this research, the “N” resolution is not directly proportional to 2<span><math><msup><mrow></mrow><mrow><mi>N</mi></mrow></msup></math></span> number of DFFs.) It uses a single clock input for synchronization to achieve high input clock frequency (f<span><math><msub><mrow></mrow><mrow><mi>clkin</mi></mrow></msub></math></span>). The DPWM has a Non-overlapping circuit to prevent shoot-through between DPWM complementary outputs during operations. The DPWM architecture has been fabricated using UMC 180-nm CMOS technology. The DPWM’s functionality and performance were validated through the measured comparisons at f<span><math><msub><mrow></mrow><mrow><mi>clkin</mi></mrow></msub></math></span> = 100, 250, 350, and 400 MHz. It achieves a maximum duty ratio of 99.6 % and output voltage of 1.79 V with 8.913 mW power dissipation at f<span><math><msub><mrow></mrow><mrow><mi>clkin</mi></mrow></msub></math></span> = 400 MHz. In addition, it has the highest f<span><math><msub><mrow></mrow><mrow><mi>clkin</mi></mrow></msub></math></span> and resolution to date, which makes it superior to prior works.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"163 ","pages":"Article 106768"},"PeriodicalIF":1.9,"publicationDate":"2025-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144365998","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Numerical analysis of single-event hardened vertical GaN CAVET with source extension and InGaN charge diversion layer 具有源扩展和InGaN电荷转移层的单事件硬化垂直GaN CAVET的数值分析

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-06-18 DOI: 10.1016/j.mejo.2025.106773

Liang Jing , Yanjun Wu , Xingyu Luo , Jingyu Shen , Shengdong Hu , Sheng Gao

引用次数: 0

62dBc SFDR 1.52 GHz output DDFS utilizing real-time DCO calibration in 65 nm CMOS for radar and communication systems 62dBc SFDR 1.52 GHz输出DDFS，采用65nm CMOS实时DCO校准，用于雷达和通信系统

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-06-16 DOI: 10.1016/j.mejo.2025.106772

Tao Zhang , Gang Dong , Shubin Liu , Jiang Wu , Jiaqi Wang , Zongguang Yu

引用次数: 0

A compact analog beamforming receiver for 8-element by 8-beam massive multi-user MIMO in 65 nm CMOS 一种用于8元8波束大规模多用户MIMO的紧凑模拟波束形成接收机

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-06-15 DOI: 10.1016/j.mejo.2025.106747

Changwei Wang , Yongjie Li , Zezheng Li , Dongwei Pang , Biao Deng , Mingjie Liu , Yan Wang , Dongfang Pan , Liguo Sun

{"title":"A compact analog beamforming receiver for 8-element by 8-beam massive multi-user MIMO in 65 nm CMOS","authors":"Changwei Wang , Yongjie Li , Zezheng Li , Dongwei Pang , Biao Deng , Mingjie Liu , Yan Wang , Dongfang Pan , Liguo Sun","doi":"10.1016/j.mejo.2025.106747","DOIUrl":"10.1016/j.mejo.2025.106747","url":null,"abstract":"<div><div>This paper presents a fully connected 8 × 8 analog beamforming receiver implemented in 65 nm CMOS technology for massive multi-user multiple-input multiple-output (MU-MIMO) systems. The design features a fully connected architecture that enables efficient hardware reuse while simultaneously supporting multiple beams. The receiver features 64 channels, each containing a programmable gain amplifier (PGA) and a phase shifter (PS) for precise amplitude and phase adjustment. The design achieves an RMS phase error of 1.12°and an RMS gain error of 0.33 dB. Measurement results show that each channel has a 3-dB RF bandwidth of 1.8 GHz centered at 8.35 GHz and a noise figure below 9.6 dB. The overall 8 × 8 architecture attains a normalized bandwidth of 11.4%, which enhances beamforming accuracy and facilitates system integration. Additionally, the design maintains a low power consumption of 28.6 mW per RX element per beam and occupies a compact silicon area of 0.25 mm<span><math><msup><mrow></mrow><mrow><mn>2</mn></mrow></msup></math></span> per RX element.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"163 ","pages":"Article 106747"},"PeriodicalIF":1.9,"publicationDate":"2025-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144308070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0