Microelectronics Journal最新文献_第4页

4H-SiC semi-superjunction IGBT with split-gate and back-side trench heterojunction for low loss and low EMI noise 采用分裂栅极和背面沟槽异质结的 4H-SiC 半超级结 IGBT，可实现低损耗和低 EMI 噪声

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-01 DOI: 10.1016/j.mejo.2025.106671

Dong Wu , Xiang Guo , Zhao Ding , Wenhan Hou

{"title":"4H-SiC semi-superjunction IGBT with split-gate and back-side trench heterojunction for low loss and low EMI noise","authors":"Dong Wu , Xiang Guo , Zhao Ding , Wenhan Hou","doi":"10.1016/j.mejo.2025.106671","DOIUrl":"10.1016/j.mejo.2025.106671","url":null,"abstract":"<div><div>In this paper, a 4H-SiC semi-superjunction insulated gate bipolar transistor (IGBT) featuring a split-gate and back-side trench heterojunction (SGTH-IGBT) is proposed to minimize turn-off loss (<em>E</em><sub>off</sub>) and suppress electromagnetic interference (EMI) noise. The SGTH-IGBT features a self-adaptive hole path (SHP) between the split-gate, enabling controlled hole storage during the on-state and rapid release during the turn-off transient. Additionally, the trench heterojunction establishes an electron extraction path to accelerate carrier removal. Compared to TFS-IGBT, the <em>E</em><sub>off</sub> of the SGTH-IGBT is reduced by 62.5 % under the same on-state voltage (<em>V</em><sub>on</sub>), while achieving a 29.7 % lower <em>V</em><sub>on</sub> than the GS-IGBT at the same <em>E</em><sub>off</sub>. Furthermore, the SGTH-IGBT reduces the Miller charge (<em>Q</em><sub>gc</sub>) by 58.2 % compared to the TFS-IGBT. At the turn-on process, SGTH-IGBT can extract a portion of the holes accumulated at the trench gate bottom. This extraction reduces the reverse displacement current (<em>I</em><sub>G_dis</sub>), thereby reducing EMI noise. In comparison to GS-IGBT and TFS-IGBT, the SGTH-IGBT demonstrates significantly better control of <em>dV/dt</em> through <em>R</em><sub>g</sub>.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106671"},"PeriodicalIF":1.9,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143759026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Temperature dependence of dynamic performance of SiC MOSFETs in a half-bridge configuration 半桥结构SiC mosfet动态性能的温度依赖性

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-01 DOI: 10.1016/j.mejo.2025.106672

Tianlu Wang , Yu Zhong , Lan Luo , Fanpeng Zeng , Ziang Zhao , Yingxin Cui , Mingsheng Xu , Xiangang Xu , Handoko Linewih , Jisheng Han

{"title":"Temperature dependence of dynamic performance of SiC MOSFETs in a half-bridge configuration","authors":"Tianlu Wang , Yu Zhong , Lan Luo , Fanpeng Zeng , Ziang Zhao , Yingxin Cui , Mingsheng Xu , Xiangang Xu , Handoko Linewih , Jisheng Han","doi":"10.1016/j.mejo.2025.106672","DOIUrl":"10.1016/j.mejo.2025.106672","url":null,"abstract":"<div><div>High-temperature robustness of switching device is crucial for the system operation reliability. Given the importance of accurate SiC MOSFET dynamic analysis in high-temperature settings, comprehensive investigations are needed. Thus, this paper delves into the dynamic characteristics of SiC MOSFETs under high temperature conditions. Firstly, a piecewise equivalent circuit model is introduced, which provides a framework for analyzing the switching behavior and the influence of reverse recovery on switching performance. Then, the roles of parameters-threshold voltage, internal gate resistance, and gate to source capacitance are explained in governing the high temperature dynamic performance of SiC MOSFETs. Through systematic testing and analysis, the switching characteristics and reverse recovery performance of three 1.2 kV SiC MOSFETs are carefully evaluated across varying temperatures. According to our study, the reverse recovery phenomenon is identified as the main cause of turn-on performance degradation at high temperatures. Furthermore, the effect of the SiC MOSFET structure on the dynamic behavior is discussed. This work discusses the impact of SiC MOSFET structure on dynamic behavior, specifically in the context of a half-bridge configuration. This assessment deepens understanding of SiC MOSFET behavior at high temperatures, guiding strategies to boost efficiency and reliability in power electronics.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"160 ","pages":"Article 106672"},"PeriodicalIF":1.9,"publicationDate":"2025-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143776330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Stress analysis and optimization of QFN solder joints under bending-torsion coupled conditions based on the SSA 基于SSA的QFN焊点弯曲-扭转耦合应力分析与优化

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-04-01 DOI: 10.1016/j.mejo.2025.106661

Jisheng Wei, Chunyue Huang, Chao Gao, Gui Wang

引用次数: 0

A novel 8T2R NVSRAM with synchronizing write and store function 具有同步写入和存储功能的新型8T2R NVSRAM

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-31 DOI: 10.1016/j.mejo.2025.106667

Bowen Su , Jueping Cai , Yuxin Zhang , Jizhang Chen , Yiding Wang

{"title":"A novel 8T2R NVSRAM with synchronizing write and store function","authors":"Bowen Su , Jueping Cai , Yuxin Zhang , Jizhang Chen , Yiding Wang","doi":"10.1016/j.mejo.2025.106667","DOIUrl":"10.1016/j.mejo.2025.106667","url":null,"abstract":"<div><div>A novel 8T2R non-volatile static randomized memory (NVSRAM) is proposed to meet accidental power-down situations by storing data into two memristors simultaneously with writing the node voltages. By shortening the writing and storing of previous NVSRAMs into one-step, the hold-on mode can be omitted and the energy consumption decreased since it is necessary to use additional control signals for inserting memristors for storage into the circuit. The initialization of memristors before writing can also be skipped. Only the power supply is needed to be recovered, and the restoration of node voltages can be achieved normally without the pre-charge of other ports. Compared with existing NVSRAMs, 8T2R NVSRAM greatly improves the circuit efficiency and reduces the power consumption by minimizing the operation steps and the required external excitation. An extra node voltage is added as a reference in 8T2R, which increases the reliability of the storage along with both memristor states. Simulations demonstrated that the proposed 8T2R can balance read margin and write margin well and has good robustness.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"160 ","pages":"Article 106667"},"PeriodicalIF":1.9,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143791014","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A 59-dB SFDR CFOA with adaptive transimpedance and driver-transistor-negative feedback for line driver in B-PLC applications 一种具有自适应跨阻和驱动器-晶体管负反馈的59 db SFDR CFOA，用于B-PLC应用中的线路驱动器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-28 DOI: 10.1016/j.mejo.2025.106657

Mingdong Li , Zhao Dong , Shalin Huang , Fang Tang

{"title":"A 59-dB SFDR CFOA with adaptive transimpedance and driver-transistor-negative feedback for line driver in B-PLC applications","authors":"Mingdong Li , Zhao Dong , Shalin Huang , Fang Tang","doi":"10.1016/j.mejo.2025.106657","DOIUrl":"10.1016/j.mejo.2025.106657","url":null,"abstract":"<div><div>This paper presents a highly linear current-feedback operational amplifier (CFOA), featuring wide bandwidth and large amplitude for line driver in broadband power line communication (B-PLC) systems. The proposed CFOA employs an adaptive transimpedance (ATI) architecture to enhance linearity across the entire amplitude range, and a driver-transistor-negative feedback (DTNF) technique to minimize crossover distortion introduced by the output stage. The prototype of the line driver chip is fabricated in a silicon-on-insulator complementary bipolar junction transistor (SOI-CBJT) process. The measured circuit bandwidth is 120 MHz, with a DC power consumption of 276 mW under a typical supply voltage of 12 V. Measurement results show that the spurious-free dynamic range (SFDR) is 59 dB for a 16-<span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>p</mi><mi>p</mi></mrow></msub></math></span> output at 1-MHz input, and 48 dB for an 8-V<span><math><msub><mrow></mrow><mrow><mi>p</mi><mi>p</mi></mrow></msub></math></span> output at 12-MHz input, driving a 100-<span><math><mi>Ω</mi></math></span> load. Over the typical amplitude and frequency range of B-PLC applications, the attenuation rates are 2.43 dB/<span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>p</mi><mi>p</mi></mrow></msub></math></span> and 2.45 dB/MHz, respectively.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106657"},"PeriodicalIF":1.9,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143759033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A single-inductor multiple-output buck/boost DC–DC converter with both suppressed self-regulation and cross-regulation via an energy storage channel 一种单电感多输出降压/升压DC-DC变换器，具有抑制自调节和通过储能通道的交叉调节

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-28 DOI: 10.1016/j.mejo.2025.106655

Hui Tong, Meigui Wang, Zhijian Chen, Yanqi Zheng

{"title":"A single-inductor multiple-output buck/boost DC–DC converter with both suppressed self-regulation and cross-regulation via an energy storage channel","authors":"Hui Tong, Meigui Wang, Zhijian Chen, Yanqi Zheng","doi":"10.1016/j.mejo.2025.106655","DOIUrl":"10.1016/j.mejo.2025.106655","url":null,"abstract":"<div><div>A single-inductor multiple-output buck/boost DC–DC converter that utilizes an energy storage channel to effectively improve the performance in both self-regulation (SR) and cross-regulation (CR) is presented in this article. With the extra channel, the energy storage and distribution method (ESDM) suppresses CR by extending charge control and SR through parallel power delivery. Additionally, the converter facilitates a seamless transition between continuous conduction mode (CCM) and low power mode (LPM) based on load conditions, thereby enhancing load capacity and overall efficiency. The converter is implemented in a standard 0.18-<span><math><mi>μ</mi></math></span>m 1.8 V/3.3 V CMOS process. Simulation results indicate that the SR of the proposed design is less than 0.056 mV/mA, achieving a 15.9<span><math><mo>×</mo></math></span> reduction compared to the conventional charge control method, while CR is less than 0.027 mV/mA, with a 10.7<span><math><mo>×</mo></math></span> reduction. The converter achieves a peak efficiency of 92.3% and maintains an efficiency of 88.2% at a light load of 1 mW.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106655"},"PeriodicalIF":1.9,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143739766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Negative capacitance double-gate MOSFET for advanced low-power electronic applications 负电容双栅MOSFET用于先进的低功耗电子应用

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-28 DOI: 10.1016/j.mejo.2025.106656

Amit Kumar , Saurabh Chaturvedi , Satyendra Kumar

{"title":"Negative capacitance double-gate MOSFET for advanced low-power electronic applications","authors":"Amit Kumar , Saurabh Chaturvedi , Satyendra Kumar","doi":"10.1016/j.mejo.2025.106656","DOIUrl":"10.1016/j.mejo.2025.106656","url":null,"abstract":"<div><div>The negative capacitance metal–oxide–semiconductor field-effect transistor (NC-MOSFET) has gained significant attention for its potential in low-power applications. This paper introduces a novel triple-material double-gate negative capacitance MOSFET (TM-DG-NC-MOSFET) architecture, analyzed through technology computer-aided design (TCAD) simulations to assess its DC, analog, linearity, and distortion performance characteristics. For comparison, a triple-material double-gate MOSFET (TM-DG-MOSFET) without the negative capacitance effect is also designed and simulated. Key device parameters are optimized for both architectures. TCAD simulation results at <span><math><msub><mrow><mi>V</mi></mrow><mrow><mi>D</mi><mi>S</mi></mrow></msub></math></span> = 0.1 V reveal that the TM-DG-NC-MOSFET achieves a subthreshold swing of 25 mV/decade, an on-state current of <span><math><mrow><mn>3</mn><mo>.</mo><mn>19</mn><mo>×</mo><mn>1</mn><msup><mrow><mn>0</mn></mrow><mrow><mo>−</mo><mn>3</mn></mrow></msup></mrow></math></span> A/<span><math><mrow><mi>μ</mi><mi>m</mi></mrow></math></span>, and a switching ratio of <span><math><mrow><mn>5</mn><mo>.</mo><mn>13</mn><mo>×</mo><mn>1</mn><msup><mrow><mn>0</mn></mrow><mrow><mn>7</mn></mrow></msup></mrow></math></span>, outperforming the baseline TM-DG-MOSFET, which exhibits a subthreshold swing of 77 mV/decade, an on-state current of <span><math><mrow><mn>0</mn><mo>.</mo><mn>83</mn><mo>×</mo><mn>1</mn><msup><mrow><mn>0</mn></mrow><mrow><mo>−</mo><mn>3</mn></mrow></msup></mrow></math></span> A/<span><math><mrow><mi>μ</mi><mi>m</mi></mrow></math></span>, and a switching ratio of <span><math><mrow><mn>1</mn><mo>.</mo><mn>34</mn><mo>×</mo><mn>1</mn><msup><mrow><mn>0</mn></mrow><mrow><mn>7</mn></mrow></msup></mrow></math></span>. Comparative analysis shows that the TM-DG-NC-MOSFET offers enhanced DC, analog, and linearity performance with reduced distortion, indicating its suitability as a promising candidate for low-power circuit applications.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106656"},"PeriodicalIF":1.9,"publicationDate":"2025-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143739445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An investigation of how circuit parameters affect the short-circuit type 2 ruggedness in FS-IGBT FS-IGBT中电路参数对短路2型坚固性影响的研究

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-27 DOI: 10.1016/j.mejo.2025.106665

Jingping Zhang , Houcai Luo , Huan Wu , Bofeng Zheng , Xianping Chen

{"title":"An investigation of how circuit parameters affect the short-circuit type 2 ruggedness in FS-IGBT","authors":"Jingping Zhang , Houcai Luo , Huan Wu , Bofeng Zheng , Xianping Chen","doi":"10.1016/j.mejo.2025.106665","DOIUrl":"10.1016/j.mejo.2025.106665","url":null,"abstract":"<div><div>Field-stop insulated gate bipolar transistors (FS-IGBTs) are extensively utilized in various power applications because of their lower conduction and switching losses. However, as application conditions become more demanding, there is an increasing need for improved reliability and ruggedness of the FS-IGBT. Short circuits are one of the most common failures of FS-IGBTs. Under these circumstances, the device may conduct unexpectedly or operate with minimal bus parasitic inductance, leading to a significant increase in the device's junction temperature. Failure to turn off the FS-IGBT promptly may result in thermal runaway and device burnout. Short-circuit type 2 (SC2) is more frequently observed in practical FS-IGBT applications than short-circuit type 1 (SC1). Nevertheless, the majority of current research primarily concentrates on SC1, with relatively limited studies on SC2 of FS-IGBTs. This study aims to investigate the circuit parameters of SC2 and comprehensively analyze the impact of each parameter on SC2. The experimental results indicate that the bus voltage <em>V</em><sub><em>DC</em></sub>, gate voltage <em>V</em><sub><em>G</em></sub>, and temperature <em>T</em><sub><em>C</em></sub> significantly affect the SC2 performance of the FS-IGBT. Therefore, a moderate decrease in <em>V</em><sub><em>DC</em></sub>, <em>V</em><sub><em>G</em></sub>, and <em>T</em><sub><em>C</em></sub> can effectively enhance the ruggedness of SC2 and the short-circuit withstand time <em>t</em><sub><em>SC</em></sub> of the device.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106665"},"PeriodicalIF":1.9,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143726099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An NMOS LDO with input pre-regulation technique for Sigma-Delta DAC with wide supply range 一种用于宽供电范围Sigma-Delta DAC的NMOS LDO输入预调节技术

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-27 DOI: 10.1016/j.mejo.2025.106666

Xingyuan Tong, Yinbo Li, Xin Xin

{"title":"An NMOS LDO with input pre-regulation technique for Sigma-Delta DAC with wide supply range","authors":"Xingyuan Tong, Yinbo Li, Xin Xin","doi":"10.1016/j.mejo.2025.106666","DOIUrl":"10.1016/j.mejo.2025.106666","url":null,"abstract":"<div><div>An NMOS low-dropout regulator (LDO) is presented for a digital-to-analog converter with wide supply range. To widen the input voltage range of the NMOS LDO, a voltage pre-regulator and a charge pump are combined. Under high-voltage supply conditions, the input pre-regulator is employed to circumvent high-voltage transistors (HVT) and to avoid standard-voltage transistors (SVT) breakdowns. When the input voltage is low, the charge pump boosts the supply voltage of the driving circuit for ensuring enough overdrive voltage of the NMOS power transistors. Besides, a suppression circuit using negative feedback technique is also proposed to reduce the effect of the output voltage fluctuations of the charge pump and reference circuits on the accuracy of the LDO. The proposed LDO is designed with 0.18 μm BCD process and occupies an active area of 1.14 mm<sup>2</sup>. It can operate with an input voltage range of 3.3–24 V with highly SVTs and provide a load current of up to 1 A while the quiescent current is only 0.81 mA. The load and line regulation of the LDO are 0.57 μV/mA and 0.78 mV/V, respectively.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106666"},"PeriodicalIF":1.9,"publicationDate":"2025-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143739764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A class-AB rail-to-rail operational amplifier with wide supply voltage and high gain 具有宽电源电压和高增益的ab类轨对轨运算放大器

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-26 DOI: 10.1016/j.mejo.2025.106643

Sikai Chen, Peng Zhang, Lumiao Zhang, Zhang Zhang

{"title":"A class-AB rail-to-rail operational amplifier with wide supply voltage and high gain","authors":"Sikai Chen, Peng Zhang, Lumiao Zhang, Zhang Zhang","doi":"10.1016/j.mejo.2025.106643","DOIUrl":"10.1016/j.mejo.2025.106643","url":null,"abstract":"<div><div>This paper presents a high-gain rail-to-rail operational amplifier architecture, characterized by its low voltage and high gain. The design incorporates a complementary PMOS and NMOS folded cascode, using a transconductance linear loop to bias the Class-AB stage for push–pull output. Furthermore, the circuit supports a wide input power supply voltage range, operating efficiently over an input voltage span of 1.8 V to 5 V. The op-amp was fabricated using a 90 nm BCD technology, with a core chip size of approximately <span><math><mrow><mn>0</mn><mo>.</mo><mn>455</mn><mspace></mspace><mo>×</mo><mspace></mspace><mn>0</mn><mo>.</mo><mn>374</mn><mspace></mspace><msup><mrow><mtext>mm</mtext></mrow><mrow><mn>2</mn></mrow></msup></mrow></math></span>. Post-simulation results reveal a DC gain of 123 dB, a gain bandwidth of 0.86 MHz, and a noise level of <span><math><mrow><mn>24</mn><mspace></mspace><mtext>nV</mtext><mo>/</mo><msqrt><mrow><mtext>Hz</mtext></mrow></msqrt><mspace></mspace><mi>@</mi><mspace></mspace><mn>10</mn><mspace></mspace><mtext>kHz</mtext></mrow></math></span> with a 1.8 V supply voltage. Measurement outcomes demonstrate a slew rate of <span><math><mrow><mn>0</mn><mo>.</mo><mn>157</mn><mspace></mspace><mtext>V</mtext><mo>/</mo><mi>μ</mi><mtext>s</mtext></mrow></math></span> under loading conditions of 20pF and <span><math><mrow><mn>10</mn><mspace></mspace><mtext>k</mtext><mi>Ω</mi></mrow></math></span>, with an output current of 1 mA and power consumption of <span><math><mrow><mn>21</mn><mo>.</mo><mn>77</mn><mspace></mspace><mi>μ</mi><mtext>A</mtext></mrow></math></span> and <span><math><mrow><mn>25</mn><mo>.</mo><mn>26</mn><mspace></mspace><mi>μ</mi><mtext>A</mtext></mrow></math></span> at 1.8 V and 5 V conditions, respectively.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106643"},"PeriodicalIF":1.9,"publicationDate":"2025-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143714739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0