Microelectronics Journal最新文献_第4页

A 28 nm Ising machine with adaptive majority voter and reduction algorithms for high-performance combinatorial optimization

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-07 DOI: 10.1016/j.mejo.2025.106621

Jingyang Chen , Zhiping Yu , Xiaolei Zhu

{"title":"A 28 nm Ising machine with adaptive majority voter and reduction algorithms for high-performance combinatorial optimization","authors":"Jingyang Chen , Zhiping Yu , Xiaolei Zhu","doi":"10.1016/j.mejo.2025.106621","DOIUrl":"10.1016/j.mejo.2025.106621","url":null,"abstract":"<div><div>The Ising model has shown outstanding potential for solving combinatorial optimization problems, but conventional processors based on the von Neumann architecture have difficulty emulating the behavior of spins in parallel. Therefore, to tackle combinatorial optimization problems efficiently, specialized processors with Ising models are required. In this work, an approximate logistic complementary spin update (ALCU) model is proposed that enhances the accuracy of the solution by 3.34% compared to the previous approximation methodology. In addition, an adaptive analog majority voter (AMV) is proposed, which can support higher interaction coefficient bit-width and more interaction spins with lower hardware overhead. Then, the Ising machine with 100 interaction spins in King’s Graph topology is implemented based on a 28 nm CMOS process. More than 67% less hardware overhead is required when compared to Ising machines based on digital adders. The coefficient precision is increased to 2.3x, and the number of interaction spins is increased to 1.6x compared to the Ising machine based on prior AMV.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106621"},"PeriodicalIF":1.9,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143619231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A VRO-based TDC with a constant timing resolution ratio between coarse-tuning and fine-tuning stages for a light sensor application

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-07 DOI: 10.1016/j.mejo.2025.106637

Jen-Chieh Liu , Jian-Sheng Li , Yan-Xun Chen , Yu-Lung Lo

引用次数: 0

Enhanced performance of p-GaN HEMT via partial etched AlGaN

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-05 DOI: 10.1016/j.mejo.2025.106627

Qingxin Liu , Shuang Wu , Kailin Ren , Luqiao Yin , Jianhua Zhang

引用次数: 0

S-ANN: Synchronous TCAD device simulation of FinFET using Artificial Neural Network

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-05 DOI: 10.1016/j.mejo.2025.106630

Yansen Liu , Xiaonian Liu , Ying Zhou , Peng Cao

{"title":"S-ANN: Synchronous TCAD device simulation of FinFET using Artificial Neural Network","authors":"Yansen Liu , Xiaonian Liu , Ying Zhou , Peng Cao","doi":"10.1016/j.mejo.2025.106630","DOIUrl":"10.1016/j.mejo.2025.106630","url":null,"abstract":"<div><div>The Fin Field-Effect Transistor (FinFET) plays a crucial role in integrated circuits due to its superior control capabilities and low leakage current. However, its complex structure often leads to substantial computational demands and significant time consumption during Technology Computer-Aided Design (TCAD) simulations. To address these challenges, we innovatively propose a synchronous TCAD device simulation model based on Artificial Neural Network (ANN) for FinFET at advanced technology nodes, abbreviated as S-ANN. This model systematically extracts FinFET characteristics under various physical sizes and bias conditions from TCAD simulations and further analyzes transient response data contained in TDR files to build a training dataset, thereby enabling effective training of the S-ANN model. Through rigorous testing and evaluation, S-ANN has demonstrated high compatibility with Sentaurus TCAD and the capability to accurately simulate TCAD electrical characteristics. In addition, Nanosheet FET was used to verified the generalization capability of the S-ANN model. Compared to traditional TCAD simulations, the S-ANN model significantly reduces both computational resource usage and simulation time, while effectively overcoming convergence problems. This advancement offers strong support for the rapid design and optimization of advanced semiconductor devices.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106630"},"PeriodicalIF":1.9,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143577945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A multi-module parallel current-sharing circuit and control strategy for brick power supplies

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-04 DOI: 10.1016/j.mejo.2025.106629

Xin Wang , Qingsong Zhao , Fanyi Meng , Keping Wang

引用次数: 0

Design of a low power LED driver with adjustable LDO

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-04 DOI: 10.1016/j.mejo.2025.106622

Binjie Shi , Zhenglin Li , Hao Fang , Jiadong Li

引用次数: 0

A new power-rail clamp circuit for on-chip electrostatic discharge protection

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-02 DOI: 10.1016/j.mejo.2025.106617

Yaping Yue , Shi Pu , Ruizhen Wu , Ronghui Hou

引用次数: 0

Garbage collection optimization with data separation for large data storage in deep learning applications

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-03-01 DOI: 10.1016/j.mejo.2025.106620

Qiang Zhou , Sirui Peng , Taoran Shen , Jie Yin , Tieli Sun , Xiaoyong Xue

{"title":"Garbage collection optimization with data separation for large data storage in deep learning applications","authors":"Qiang Zhou , Sirui Peng , Taoran Shen , Jie Yin , Tieli Sun , Xiaoyong Xue","doi":"10.1016/j.mejo.2025.106620","DOIUrl":"10.1016/j.mejo.2025.106620","url":null,"abstract":"<div><div>Deep learning has revolutionized numerous domains, creating an urgent need for storage systems capable of handling massive datasets and the intensive computational demands inherent to these workloads. Solid-State Drives (SSDs), known for their fast random access, low power consumption, and shock resistance, have emerged as a preferred storage medium in this context. However, traditional SSDs face critical challenges, including garbage collection (GC) overhead, write amplification, and inefficiencies in the software storage stack, stemming from the intrinsic characteristics of NAND flash and limitations in the existing storage ecosystem. These challenges underscore the necessity for specialized SSD controller chip designs tailored for deep learning workloads, addressing performance bottlenecks and optimizing data management to meet the unique demands of AI-driven applications. In this work, we implemented an open-channel SSD (OCSSD) based on a Xilinx FPGA, which can effectively alleviate the above-mentioned issues by exposing the structural characteristics of NAND flash to the host. To mitigate the performance cliff of I/O requests during GC operations, the link distance for data transmission is shortened by decoupling the host end and the device end. Moreover, the valid data migration and the GC operation frequency are both dramatically reduced by detecting and separating hot data and cold data to improve the overall performance of the SSD system. To verify the superiority of our design, we build a test platform through hardware and software co-design. The experimental results show that random read and random write bandwidth are increased by 159.7 % and 25.3 % compared to the mainstream SSDs, respectively. The latency of a single GC operation is reduced by an average of 12.64 % and the GC frequency is lowered by up to 64.8 %.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"158 ","pages":"Article 106620"},"PeriodicalIF":1.9,"publicationDate":"2025-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143549259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A high speed adaptive reflection cancellation equalization circuit with Floating Tap FFE and Loop-Refactored DFE for ADC-DSP-based wireline receiver

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-27 DOI: 10.1016/j.mejo.2025.106612

Cewen Liu , Xingyun Qi , Fangxu Lv, Qiang Wang, Liquan Xiao, Xiaoyue Hu, Chaolong Xu, Zhouhao Yang, Meng Li, Mingche Lai

{"title":"A high speed adaptive reflection cancellation equalization circuit with Floating Tap FFE and Loop-Refactored DFE for ADC-DSP-based wireline receiver","authors":"Cewen Liu , Xingyun Qi , Fangxu Lv, Qiang Wang, Liquan Xiao, Xiaoyue Hu, Chaolong Xu, Zhouhao Yang, Meng Li, Mingche Lai","doi":"10.1016/j.mejo.2025.106612","DOIUrl":"10.1016/j.mejo.2025.106612","url":null,"abstract":"<div><div>High speed communication networks depend on higher data rates for bandwidth expansion, but face challenges in maintaining signal integrity when data rates exceed 100 Gb/s due to ISI and reflection, which hinder transmission speed advancements. This paper proposes the design of an adaptive reflection cancellation circuit for high-speed 4-level pulse amplitude (PAM4) serializer-deserializer (Serdes) receiver based on analog-to-digital converter (ADC) + digital signal processing (DSP) architecture. The proposed parallel Floating Tap Feedforward equalization(FT-FFE) effectively mitigates the impact of reflection without the need for a large number of equalizers, thereby reducing power consumption overhead. A Loop-Refactored decision feedback equalizer (LR-DFE) is implemented to mitigate timing constraints in ADC-DSP based high-speed wireline receivers, improving system performance and timing reliability. The tap coefficients are adaptively updated in combination with the Least Mean Square (LMS) algorithm. Simulation and FPGA platform validation results demonstrate that at a data rate of 56 Gb/s, the bit error rate(BER) is below 1e-12 through a channel with 39 dB insertion loss(IL).</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106612"},"PeriodicalIF":1.9,"publicationDate":"2025-02-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143562046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Parasitic-induced multi-zero generation and port-fusion compact filter based on 3-D through-silicon via technology

IF 1.9 3区工程技术

Microelectronics Journal Pub Date : 2025-02-27 DOI: 10.1016/j.mejo.2025.106618

Xiangkun Yin, Xiangyu Ma, Nairong Liu, Libo Qian, Tao Zhang, Qijun Lu, Zhangming Zhu

引用次数: 0