A QNU hardened latch design with low cost high stability and high performance

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-09-15 DOI:10.1016/j.mejo.2025.106896

Zhengfeng Huang , Xinyu Jiang , Linya Qiu , Yuxin Zhu , Can Liu , Huaguo Liang , Yiming Ouyang , Tianming Ni

引用次数: 0

Abstract

With the rapid development of integrated circuit technology, the sensitivity of latches to Multiple Node Upsets (MNU) induced by charge sharing has significantly increased, and this phenomenon has become a core issue affecting reliability in nanoscale integrated circuits. This paper proposes a high stability, high-performance, low-cost quadruple-node-upset (QNU) tolerant latch (DUAL-RDTL), which achieves complete QNU tolerance through the configuration of two DNU recovery latches (RDTL) and three C-elements at the output stage. HSPICE simulation results under 22 nm PTM technology demonstrate that compared with existing radiation hardened latches (QNUTL, SEI-QNUTL, 4NUHL), the DUAL-RDTL achieves average reductions of 44.69 % in power consumption, 7.09 % in delay, and 49.01 % in Power-Delay Product (PDP), while exhibiting the best stability against PVT (Process, Voltage, Temperature) variations.

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一种低成本、高稳定性和高性能的QNU硬化闩锁设计

随着集成电路技术的快速发展，锁存器对由电荷共享引起的多节点扰流（MNU）的敏感性显著提高，这一现象已成为影响纳米级集成电路可靠性的核心问题。本文提出了一种高稳定、高性能、低成本的四节点干扰容忍锁存器（DUAL-RDTL），该锁存器通过在输出阶段配置两个DNU恢复锁存器（RDTL）和三个c元来实现完全的QNU容忍。在22 nm PTM技术下的HSPICE仿真结果表明，与现有的辐射硬化锁存器（QNUTL、SEI-QNUTL、4NUHL）相比，DUAL-RDTL的功耗平均降低44.69%，延迟平均降低7.09%，功率延迟平均降低49.01%，同时对PVT （Process, Voltage, Temperature, Process, Voltage, Temperature）变化表现出最佳的稳定性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.