A reliability-noise-delay quantification method for APUF physical modeling and CRPs screening

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-09-17 DOI:10.1016/j.mejo.2025.106895

Zhengfeng Huang , Ruixiang Liu , Zezheng Wang , Yanrong Zhu , Jingchang Bian , Zhao Yang , Yingchun Lu , Yiming Ouyang , Huaguo Liang , Tianming Ni

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引用次数: 0

Abstract

Arbiter Physical Unclonable Functions (APUFs), widely used strong PUFs, are highly sensitive to environmental noise, yet the quantitative link between noise and reliability remains unclear. This paper introduces a Reliability-Noise-Delay (RND) quantification method grounded in statistical analysis of the APUF delay model. By modeling noise, we uncover CRP instability patterns under varying noise levels and derive a closed-form relationship between reliability and noise. Leveraging RND, the delay difference between last-stage paths is calculated without extra hardware by using environmental noise measurements and CRP reliability. We develop an efficient n-stages APUF modeling approach requiring only n+1 CRPs with known reliability, significantly reducing computational complexity and resource demands compared to conventional machine-learning techniques. Furthermore, we propose a screening strategy to identify high- and low-reliability CRPs: at a noise level of 0.15, low-reliability CRP reliability drops from 75 % (random) to 57 %, while high-reliability CRPs reach 99 %. Our method offers an effective tool for APUF modeling and optimization in noisy environments.

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一种用于APUF物理建模和crp筛选的可靠性-噪声-延迟量化方法

仲裁者物理不可克隆函数（Arbiter Physical unclable Functions, APUFs）是一种广泛使用的强PUFs，对环境噪声非常敏感，但噪声与可靠性之间的定量联系尚不清楚。本文介绍了一种基于APUF延迟模型统计分析的可靠性-噪声-延迟（RND）量化方法。通过对噪声进行建模，我们揭示了CRP在不同噪声水平下的不稳定性模式，并推导出可靠性与噪声之间的封闭关系。利用RND，通过使用环境噪声测量和CRP可靠性，无需额外硬件即可计算最后阶段路径之间的延迟差。我们开发了一种高效的n阶段APUF建模方法，只需要n+1个已知可靠性的crp，与传统的机器学习技术相比，显着降低了计算复杂性和资源需求。此外，我们提出了一种筛选策略来识别高可靠性和低可靠性CRP：在噪声水平为0.15时，低可靠性CRP的可靠性从75%（随机）下降到57%，而高可靠性CRP达到99%。该方法为噪声环境下的APUF建模和优化提供了有效的工具。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.