1 μ a, 25 ppm/°C， PVT弹性无电阻CMOS电流基准

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-09-23 DOI:10.1016/j.mejo.2025.106894

César Casañas , Atila Alvandpour , Alireza Saberkari , André F. Ponchet , Robson Moreno , Osamu Saotome , Ingemar Söderquist , Lucas Compassi-Severo

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引用次数: 0

摘要

本文提出了一种无电阻电流基准，对过程、电压和温度（PVT）变化具有鲁棒性。温度补偿是通过将比例-绝对温度（PTAT）元件与互补-绝对温度（CTAT）相结合来实现的，两者都是通过自级联编码MOSFET （SCM）电路产生的。采用跨导效率（gm/ID）方法确定器件尺寸和反转区域。采用65nm CMOS技术设计，所提出的电流基准占用0.032 mm2的布局面积。布局后仿真表明，平均输出电流为1.04μA（标称情况），标准差为9 nA，温度系数（TC）为25 ppm/°C（超过- 40°C至120°C），温度变化为1.3%。此外，该电路的电源抑制比（PSRR）为47.5 dB，线路灵敏度（LS）为14% /V，平均功耗为4.92 μW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An 1-μA, 25 ppm/°C, PVT resilient resistor-less CMOS current reference

This paper presents a resistor-less current reference robust against process, voltage, and temperature (PVT) variations. The temperature compensation is achieved by combining a proportional-to-absolute-temperature (PTAT) component with its complementary-to-absolute-temperature (CTAT) counterpart, both generated through self-cascode MOSFET (SCM) circuits. The transconductance efficiency (

g_{m} / I_{D}

) methodology is employed for device sizing and define the inversion region. Designed in 65 nm CMOS technology, the proposed current reference occupies a layout area of 0.032

{mm}^{2}

. Post-layout simulations demonstrate a mean output current of

1.04 μ A

(nominal case) with a standard deviation of 9 nA, a temperature coefficient (TC) of 25 ppm/°C (over −40 °C to 120 °C), and a temperature variation of 1.3%. Additionally, the circuit achieves a power supply rejection ratio (PSRR) of 47.5 dB, a line sensitivity (LS) of 14 %/V, and a average power dissipation of 4.92

μ

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.