Load-driven inductive peaking design for broad band continuous-time linear equalizer

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Journal Pub Date : 2025-09-05 DOI:10.1016/j.mejo.2025.106873

Miao Zhang , Ruidong Li , Xiaoteng Zhao , Xianting Su , Zhicheng Dong , Zekai Yang , Hongyu Su , Hongzhi Liang , Yukui Yu , Shubin Liu

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Abstract

This article presents modeling and analysis of several wideband current-mode logic (CML) continuous-time linear equalizers (CTLEs), including series peaking, shunt peaking, T-coil peaking, and bridged-shunt T-coil peaking architectures. Theoretical analysis reveals the peaking gain-bandwidth product (PGBW) of each structure. The series peaking configuration achieves the highest PGBW when the parasitic capacitance C_D is comparable to the load capacitance C_L, corresponding to larger input transistor sizes. In contrast, the bridged-shunt T-coil peaking structure delivers superior PGBW performance when C_D is significantly smaller than C_L. Based on these modeling insights, an analog front-end (AFE) circuit is designed in 28-nm CMOS technology for a 112-Gb/s PAM-4 medium-reach (MR) receiver (RXs), targeting scenarios where C_D is relatively small. The proposed AFE adopts a bridged-shunt T-coil peaking structure to extend the bandwidth. Post-layout simulations demonstrate that the proposed AFE achieves a boost gain of up to 21.5-dB dissipating 43.8 mW at a 0.9-V supply, achieving larger than 28-GHz bandwidth within the area of 0.06 mm².

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负载驱动的宽带连续时间线性均衡器电感峰值设计

本文介绍了几种宽带电流模式逻辑（CML）连续时间线性均衡器（ctls）的建模和分析，包括串联峰值、分流峰值、t线圈峰值和桥接分流t线圈峰值架构。理论分析揭示了每种结构的峰值增益带宽积（PGBW）。当寄生电容CD与负载电容CL相当时，串联峰值配置可实现最高的PGBW，对应于更大的输入晶体管尺寸。相比之下，当CD明显小于CL时，桥接分流t线圈峰值结构提供了优越的PGBW性能。基于这些建模见解，针对CD相对较小的场景，采用28纳米CMOS技术为112 gb /s PAM-4中距（MR）接收器（RXs）设计了模拟前端（AFE）电路。本文提出的AFE采用桥接分流t圈调峰结构来扩展带宽。布局后仿真表明，所提出的AFE在0.9 v电源下实现了高达21.5 db的升压增益，功耗为43.8 mW，在0.06 mm2的面积内实现了大于28 ghz的带宽。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.