A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator

This article presents a 56 Gb/s quarter-rate four-level pulse-amplitude modulation (PAM4) clock and data recovery (CDR) circuit. The proposed slope-sampling phase detector (PD) combines the slope of the data sampling point with 3-bit input pattern sequence to achieve a superior phase-detection probability of 7/16 while utilizing only four comparators per unit interval (UI). Additionally, a phase interpolator (PI) capable of simultaneously generating four-phase orthogonal clocks is proposed, serving as a high linearity, compact multiphase clock generator (MPCG). Based on 28 nm CMOS process, the architecture demonstrates an energy efficiency of 0.36 pJ/bit at 56 Gb/s input data rate from post-layout simulations. The simulated jitter tolerance at the bit error rate (BER) of <10⁻¹² exceeds 0.4 UI_pp @ 50 MHz, while the root mean square (RMS) jitter of the recovered 7 GHz clock is 683.4 fs.