A power-iteration-based beamformer for large-scale antenna arrays

Beamforming with a large-scale antenna array is one of the enabling techniques for communications in high frequencies. The related computational overhead, which arises from the sharply increased complexity of algorithmic computation and control logic due to the higher dimension of the spatial covariance matrix, is a major impediment to scaling up the antenna array and thereby improving beamforming performance. This paper presents the power-iteration-based beamforming algorithm and the hardware implementation that are well suited for the applications to large-scale antenna arrays. In general, the power iteration method converges slowly. However, we find that the slow convergence has minimal effect on the beamforming performance. This fact enables convergence-less termination of the beamforming algorithm, and hence contributes to significant reduction in the computational complexity. To deal with large-scale antenna arrays, the inherent data Hermitian symmetry property is also utilized for memory compression, reducing the memory cost nearly by half. In the meantime, the dedicated addressing scheme is provided for parallel data access without memory conflict. Our design is layouted in a 22-nm CMOS technology, supporting 32 to 1024 antenna elements, integrating 6277K gates in an area of 4.97 mm², and dissipating 159 mW at 600MHz. It outperforms the state-of-the-art results in the scalability to support large-scale antenna arrays, and can achieve high energy efficiency, too.