A linear chirp generator with 2nd DPD technique based on a Type-III SPLL

This paper presents a PLL-based frequency synthesizer tailored for linear chirp signal generation. By integrating a second-order digital predistortion (DPD) algorithm within a two-point modulation (TPM) scheme, the proposed design achieves both wide chirp bandwidth and high chirp rate concurrently. A Type-III PLL architecture is employed to leverage its intrinsic capability of accurately tracking linear frequency ramps. When combined with the DPD scheme, this approach substantially reduces the number of least-mean-square (LMS) calibration branches required for nonlinear distortion correction, thereby lowering hardware complexity while preserving high-order linearization performance. Fabricated in a 65-nm CMOS process, the chirp generator produces a sawtooth waveform with a 1.7 GHz bandwidth and a chirp rate of 332 MHz/μs. Simulation results demonstrate an RMS frequency error of 186.25 kHz, corresponding to only 0.0109 % of the full chirp bandwidth.