Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting最新文献

{"title":"Dependence of thermal resistance on ambient and actual temperature","authors":"J. Paasschens, S. Harmsma, R. van der Toorn","doi":"10.1109/BIPOL.2004.1365754","DOIUrl":"https://doi.org/10.1109/BIPOL.2004.1365754","url":null,"abstract":"We investigate the temperature dependence of thermal resistance. We extract the thermal resistance as a function of ambient temperature. The increase of thermal resistance due to self-heating leads to a non-linear relation between temperature and power dissipation. We show how to implement this in a compact model and what its effect is on simulations at high power dissipation.","PeriodicalId":447762,"journal":{"name":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131613855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fully-integrated WCDMA direct conversion SiGeC BiCMOS receiver","authors":"P. Garcia, B. Pellat, J. Blanc, P. Persechini, V. Knopik, L. Baud, F. Goussin, D. Thevenet, S. Majcherczak, F. Reaute, O. Richard, P. Conti, B. Szelag, D. Belot","doi":"10.1109/BIPOL.2004.1365759","DOIUrl":"https://doi.org/10.1109/BIPOL.2004.1365759","url":null,"abstract":"This paper describes a WCDMA direct conversion receiver which has been integrated in a BiCMOS SiGe-carbon process featuring 0.25 /spl mu/m/f/sub T/=60 GHz bipolar transistors. This receiver includes an integrated RF-front-end with local oscillator quadrature generator, 5/sup th/ order Butterworth analog baseband lowpass filter (LPF) and variable gain amplifier (VGA), cut-off frequency calibrator, DAC for DC-offset calibration, serial bus interface and voltage and current reference generators. In the high/low gain modes, this device consumes 25 mA and 20 mA respectively with 2.7 V power supply. The die is wire bonded directly on the validation board. Within the receive band, the measurements show 51 dB of overall gain, NF=5 dB, IIP3= -9 dBm, ICP1 = -15dBm.","PeriodicalId":447762,"journal":{"name":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120904970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A wideband fully integrated 0.25/spl mu/m BiCMOS 5GHz medium power amplifier","authors":"M. Vaiana, G. Gramegna, M. Paparo","doi":"10.1109/BIPOL.2004.1365808","DOIUrl":"https://doi.org/10.1109/BIPOL.2004.1365808","url":null,"abstract":"A wideband 4.2GHz-5.6GHz balanced Medium Power Amplifier has been designed in a 0.2Spm SiGe:C bipolar process. The two stage amplifier is housed in a VFQF’F”20 package with integrated inputloutput matcbing networks and onboard printed rat-race balnns. A saturated output power of 16dBm has been measured with a small signal gain of IS.2dB at SGHz with a total current consumption of llOmA from a 2.4V supply voltage at ambient temperature. The measured 3dB bandwidth is IIGHz, the best value ever reported in literature for a fully integrated medium PA housed in a standard padage for mass production witb DO external components required for inputloutput matching. The die size is 1.4~1.750 m d .","PeriodicalId":447762,"journal":{"name":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123197805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Performance trade-offs and optimization of low side low voltage integrated FETs","authors":"S. Pendharkar, R. Ramanathan, T. Efland, L. Zheng","doi":"10.1109/BIPOL.2004.1365769","DOIUrl":"https://doi.org/10.1109/BIPOL.2004.1365769","url":null,"abstract":"The performance trade-offs associated with low side low voltage integrated thin resurf LDMOS (lateral FET) devices are discussed. It is shown that, in junction isolation (JI) technologies using a p-substrate, a suitably optimized isolated drain LDMOS device architecture offers significant benefits over the non-isolated drain low side device, especially for applications which do not require true unclamped inductive switching capability.","PeriodicalId":447762,"journal":{"name":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123600682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Analytical explanation of different RF characteristics exhibited with common-emitter and common-base bipolar transistors [SiGe HBT example]","authors":"N. Jiang, Guogong Wang, Z. Ma","doi":"10.1109/BIPOL.2004.1365758","DOIUrl":"https://doi.org/10.1109/BIPOL.2004.1365758","url":null,"abstract":"For the first time, the differences of RF characteristics exhibited by bipolar transistors between common-emitter and common-base configurations, under different stability conditions, are analytically elucidated. The analyses are verified with measured results from SiGe heterojunction bipolar transistors. These analyses markedly advocate that different configurations should be used at different amplification frequencies in order to maximize the RF performance potential of bipolar transistors.","PeriodicalId":447762,"journal":{"name":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121495278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Calibration-free on-chip inductor coupling experiment with injection-lockable VCOs","authors":"P. Popplewell, R. Amaya, M. Cloutier, C. Plett","doi":"10.1109/BIPOL.2004.1365795","DOIUrl":"https://doi.org/10.1109/BIPOL.2004.1365795","url":null,"abstract":"A novel experiment is presented which makes use of injection-lockable bipolar oscillators to measure on-chip coupling between integrated inductors. The experiment is fast, accurate and unique In that no matching, probe de-embedding or calibration is necessary as the ratio of two on-chip signals is measured to yield the results. Theoretical and simulated models of injectionlocked oscillators and inductor coupling are discussed and compared to results measured using the test chip to Validate the experiment. Results indicate about -55 dB of Coupling between two inductors spaced 175 pm apart. K e p m d Coupling Circuits, Electromagnetic Coupling, Inductors, Injection Locked Oscillators.","PeriodicalId":447762,"journal":{"name":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125989183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wideband lumped scalable modeling of monolithic stacked transformers on silicon","authors":"T. Biondi, A. Scuderi, E. Ragonese, G. Palmisano","doi":"10.1109/BIPOL.2004.1365796","DOIUrl":"https://doi.org/10.1109/BIPOL.2004.1365796","url":null,"abstract":"A lumped model for monolithic stacked transformers on silicon is presented. It employs a novel topology that combines tbe simplicity of lumped models aud the accuracy of distributed networks. Model parameters are calculated by means of closed-form expressions using geometrical and technological data. The accuracy of the proposed model is demonstrated by comparing simulations with on-wafer experimental measurements of several stacked transformers. The self-resonance frequency is used as a figure of merit to test the performance at very high frequencies. Moreover, the geometrical scalability is verified employing the S-parameters of transformers with different layout parameters and over a wide frequency range.","PeriodicalId":447762,"journal":{"name":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132750544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 675 /spl mu/W 5 GHz low-voltage BiCMOS synchronized ring oscillator based prescaler","authors":"O. Mazouffre, H. Lapuyade, J.-B. Bdgueret, Andreia Cathelin, Didier Belot, Y. Devall","doi":"10.1109/BIPOL.2004.1365791","DOIUrl":"https://doi.org/10.1109/BIPOL.2004.1365791","url":null,"abstract":"This paper presents the design and the experimental measurements of a 5 GHz divide-by-4 prescaler for 802.11a and HiperLAN2 applications. The presented circuit is implemented in a 0.25μm BiCMOS SiGe process from STMicroelectronics. The prescaler is optimized for low power operation. It uses a Synchronized Ring Oscillator architecture based on two low-voltage differential bipolar latches with PMOS loads. The prescaler draws 520 μA from a 1.3 V power supply, its operating frequency is from 4.7 GHz to 6.8 GHz with a sensitivity of -10 dBm, and its efficiency is about 10 GHz/mW.","PeriodicalId":447762,"journal":{"name":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","volume":"335 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133224719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A 250 Gb/s power efficient fiber optic chipset for optical backplanes","authors":"G. Flower, Lik-Khai Chia, E. Ali, B. Lernoff","doi":"10.1109/BIPOL.2004.1365801","DOIUrl":"https://doi.org/10.1109/BIPOL.2004.1365801","url":null,"abstract":"A 48-channel fiber optic transmitter and receiver have been designed for very reach very high bandwidth use in processor-to-cache connections in order to remove the bandwidth bottleneck. Each of the chips dissipates about .75 watts and operates from 2.5V. Introduction: Design : High-performance box-level systems based upon highly scaled CMOS VLSI, highperformance multi-chip modules and PC boards are reaching a level of performance that is exposing a severe bottleneck at the edgeconnection of the board-to-board interconnect. Electrical interconnections are having difficulty providing the needed edge-connection bandwidth densities (measured in Gb/s/cm) [I]. Applications requiring the movement of 1-10 Terabitsls of data to be moved less than IO meters exist in instrumentation, computer, and router applications and are increasing. In addition, thermal issues are reaching a critical level in systems which can generally not afford the extra cost of exotic cooling techniques such as thermoelectric coolers. Electrical connections based upon FR4 boards, traces and connectors also face the challenges associated with skin losses, dielectric losses and crosstalk. Optical interconnections based upon parallel optical fibers, vertical-cavity surfaceemiting lasers (VCSELs), modem optical packaging and flip chip techniques can alleviate this problem[2]. An optical module can launch light directly onto a parallel multimode ribbon fiber using very small VCSELs eliminating the edge connector congestion and the losses associated with high-speed transmission lines on FR4 and connectors. Such a link can be designed to emphasize power efficiency achieving a high rate of data transfer per bit. A fiber optic chipset and package has been designed to address this type of data bottleneck. Both the transmitter and the receiver chip consist of 48 channels capable of operating at a data rate up to 5.21Gbis. The overall design makes use of a combination of parallel optics technology and coarse wave division multiplexing (CWDM) to launch and receive 48 channels of optical data in a standard 12-wide 50-micron core multimode parallel optical fiber. Each fiber attached to an optical multiplexer and demultiplexer (one at each end) and carrying 4 different wavelengths of light. Figure1 shows a diagram of the packaging assembly which uses a chip mounted enclosure (CME) similar to that used in [2]. The silicon transmitter chip has four 1x12 arrays of VCSELs flip chipped onto its surface. Each array of lasers has a distinct wavelength with a wavelength separation of 301x11 and an average wavelength of 1 0 3 5 ~ 1 . The wavelengths chosen are longer than are often used (e.g. 850nm) because this allows the light to be emitted through the substrate and directly into the optical multiplexer. The multiplexer combines 4 wavelengths and steers the output into one of the 12 fibers. Guide pins on the assembly allow the connection between the PMOSA and an MT Ferrule. At the other end of the fiber ","PeriodicalId":447762,"journal":{"name":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131365447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A modular, low-cost SiGe:C BiCMOS process featuring high-f/sub T/ and high BV/sub CEO/ transistors","authors":"D. Knoll, B. Heinemann, R. Barth, K. Blum, J. Borngraber, J. Drews, K. Ehwald, G. Fischer, A. Fox, T. Grabolla, U. Haak, W. Hoppner, F. Korndorfer, B. Kuck, S. Marschmeyer, H. Richter, H. Rucker, P. Schley, D. Schmidt, R. Scholz, B. Senapati, B. Tillack, W. Winkler, D. Wolansky, C. Wolf, H. Wulf, Y. Yamamoto, P. Zaumseil","doi":"10.1109/BIPOL.2004.1365790","DOIUrl":"https://doi.org/10.1109/BIPOL.2004.1365790","url":null,"abstract":"We demonstrate a BiCMOS process which uses only 22 mask steps to fabricate four types of SiGe:C HBTs, in combination with a triple-well, 2.5V CMOS core and a full menu of passive elements. Key process feature is a 2-mask HBT module. We show that transistors with peak fT values ranging from 3OGHz (@ 7V BV,) up to 130GHz (@ 2.1V BVczo) can he fabricated with this low-cost module. Among the passives are varactors, polysilicon resistors, and a 2fF/pmz MIMsapacitor. Five layers of AI are available, including 2pm and 3pm thick upper layers. SOC ability of the process is demonstrated by a 1MSRAM yield of typically 70%.","PeriodicalId":447762,"journal":{"name":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130332766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}