A 250 Gb/s power efficient fiber optic chipset for optical backplanes

A 48-channel fiber optic transmitter and receiver have been designed for very reach very high bandwidth use in processor-to-cache connections in order to remove the bandwidth bottleneck. Each of the chips dissipates about .75 watts and operates from 2.5V. Introduction: Design : High-performance box-level systems based upon highly scaled CMOS VLSI, highperformance multi-chip modules and PC boards are reaching a level of performance that is exposing a severe bottleneck at the edgeconnection of the board-to-board interconnect. Electrical interconnections are having difficulty providing the needed edge-connection bandwidth densities (measured in Gb/s/cm) [I]. Applications requiring the movement of 1-10 Terabitsls of data to be moved less than IO meters exist in instrumentation, computer, and router applications and are increasing. In addition, thermal issues are reaching a critical level in systems which can generally not afford the extra cost of exotic cooling techniques such as thermoelectric coolers. Electrical connections based upon FR4 boards, traces and connectors also face the challenges associated with skin losses, dielectric losses and crosstalk. Optical interconnections based upon parallel optical fibers, vertical-cavity surfaceemiting lasers (VCSELs), modem optical packaging and flip chip techniques can alleviate this problem[2]. An optical module can launch light directly onto a parallel multimode ribbon fiber using very small VCSELs eliminating the edge connector congestion and the losses associated with high-speed transmission lines on FR4 and connectors. Such a link can be designed to emphasize power efficiency achieving a high rate of data transfer per bit. A fiber optic chipset and package has been designed to address this type of data bottleneck. Both the transmitter and the receiver chip consist of 48 channels capable of operating at a data rate up to 5.21Gbis. The overall design makes use of a combination of parallel optics technology and coarse wave division multiplexing (CWDM) to launch and receive 48 channels of optical data in a standard 12-wide 50-micron core multimode parallel optical fiber. Each fiber attached to an optical multiplexer and demultiplexer (one at each end) and carrying 4 different wavelengths of light. Figure1 shows a diagram of the packaging assembly which uses a chip mounted enclosure (CME) similar to that used in [2]. The silicon transmitter chip has four 1x12 arrays of VCSELs flip chipped onto its surface. Each array of lasers has a distinct wavelength with a wavelength separation of 301x11 and an average wavelength of 1 0 3 5 ~ 1 . The wavelengths chosen are longer than are often used (e.g. 850nm) because this allows the light to be emitted through the substrate and directly into the optical multiplexer. The multiplexer combines 4 wavelengths and steers the output into one of the 12 fibers. Guide pins on the assembly allow the connection between the PMOSA and an MT Ferrule. At the other end of the fiber a similar assembly awaits the light. Each of the 12 fibers encounters an optical demultiplexer which separates the 4 wavelengths and steers them to 0-7803-8618-3/04/$20.00 02004 IEEE 265