{"title":"低侧低压集成场效应管的性能权衡与优化","authors":"S. Pendharkar, R. Ramanathan, T. Efland, L. Zheng","doi":"10.1109/BIPOL.2004.1365769","DOIUrl":null,"url":null,"abstract":"The performance trade-offs associated with low side low voltage integrated thin resurf LDMOS (lateral FET) devices are discussed. It is shown that, in junction isolation (JI) technologies using a p-substrate, a suitably optimized isolated drain LDMOS device architecture offers significant benefits over the non-isolated drain low side device, especially for applications which do not require true unclamped inductive switching capability.","PeriodicalId":447762,"journal":{"name":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Performance trade-offs and optimization of low side low voltage integrated FETs\",\"authors\":\"S. Pendharkar, R. Ramanathan, T. Efland, L. Zheng\",\"doi\":\"10.1109/BIPOL.2004.1365769\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The performance trade-offs associated with low side low voltage integrated thin resurf LDMOS (lateral FET) devices are discussed. It is shown that, in junction isolation (JI) technologies using a p-substrate, a suitably optimized isolated drain LDMOS device architecture offers significant benefits over the non-isolated drain low side device, especially for applications which do not require true unclamped inductive switching capability.\",\"PeriodicalId\":447762,\"journal\":{\"name\":\"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting\",\"volume\":\"58 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-12-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BIPOL.2004.1365769\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIPOL.2004.1365769","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Performance trade-offs and optimization of low side low voltage integrated FETs
The performance trade-offs associated with low side low voltage integrated thin resurf LDMOS (lateral FET) devices are discussed. It is shown that, in junction isolation (JI) technologies using a p-substrate, a suitably optimized isolated drain LDMOS device architecture offers significant benefits over the non-isolated drain low side device, especially for applications which do not require true unclamped inductive switching capability.
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