Performance trade-offs and optimization of low side low voltage integrated FETs

Abstract

The performance trade-offs associated with low side low voltage integrated thin resurf LDMOS (lateral FET) devices are discussed. It is shown that, in junction isolation (JI) technologies using a p-substrate, a suitably optimized isolated drain LDMOS device architecture offers significant benefits over the non-isolated drain low side device, especially for applications which do not require true unclamped inductive switching capability.