{"title":"Current carry capacity characterization for high performance system on chip packages","authors":"N. Ying, Wong Wui Weng","doi":"10.1109/EPTC.2015.7412285","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412285","url":null,"abstract":"System on Chip (SoC) technology is rapidly evolved across high power workstations to low power tablets. As complex SoC further integrates several hardware functionalities, the system-level on-chip architecture is emerging as a significant source of power consumption. Improving current carry capacity (CCC) of existing packages can be one of factors to enhance power consumption with minimum cost. To deal with thermal effects of joule heating in a typical high pin count organic substrate of today SOC, a test vehicle was energized with various current levels and the correspondent temperature rise was measured. This paper introduces an effective current carry capacity characterization method to investigate the ability of pins to support higher current levels. It can be achieved by setting the test environment resembled to application conditions and to challenge operating limit which defined by a conservative approach. Up to 20% improvement in higher current carrying capacity was observed, which could ultimately translate into performance and power gain in today SOC with a complex package.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117267443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Dynamic simulation of die pickup from wafer tape by a multi-disc ejector using peel-energy to peel-velocity coupling","authors":"S. Behler","doi":"10.1109/EPTC.2015.7412268","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412268","url":null,"abstract":"A 2D simulation of thin die peeling from wafer tape is presented for a Multi Disc ejection system. The simulation models the dynamics of peeling, and visualizes time-dependency of peel front propagation and target die stress. It is based on a series of static snapshots, stringed together like a movie. A coupling of peel energy and peel velocity is defined. This allows to calculate the geometry of the actual snapshot by the peel energy of the preceding one. As a result, experimental data of a peel process can be verified. It is shown, why an increase in disc velocity leads to a slow-down of peel front propagation, and thus to a pickup failure.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"162 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123132938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Development of compliant Cu pillar for flip chip package","authors":"B. Jung, F. Che, Jong-Kai Lin","doi":"10.1109/EPTC.2015.7412352","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412352","url":null,"abstract":"A compliant flip chip bump design compromises of a polymer core inside a Cu pillar, a polymer encapsulated Cu pillar and the process flow to make such bumps for fine pitch flip chip package is proposed in this study. Both polymer core and polymer encapsulated Cu pillar structures are able to provide the compliance to the Cu pillar structure and reduce stress on low K dielectric layers. A structural analysis showed the polymer encapsulated bump and polymer core bump reduce the low K dielectric stress by 35% and 20%, respectively, compared to conventional Cu pillar structure. Also both compliant bump structures (polymer encapsulated and polymer core bump) increase solder joint thermal cycle life time by 55% and 30%, respectively.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123630414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A methodology for package to test interaction study","authors":"Han Guan Tan, L.P. Ng, Jie Huang, A. Yeo","doi":"10.1109/EPTC.2015.7412267","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412267","url":null,"abstract":"A mechanical test methodology is developed to examine the lead robustness of the IC package during final test. It is important to eliminate defective package leads during testing so that the risk in the downstream processability can be reduced. A micro-mechanical tester is employed to determine the deformation behaviour of the package leads follow by its deflection measurement using an optical profiler. Different test conditions such as force and number of touch downs are simulated and evaluated for different leaded package types. The experimental results are then compared and discussed with the actual data from the package final test. A correlation is established, where design and process guideline can be recommended for a robust package leads for testing. In essence, this methodology is able to provide an understanding on the IC package lead structural behaviour at the final package test, thus provides an examination platform in Package to Test design and process optimization.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122765101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Microball and thicker Cu Pad: A substrate solution for better package reliability and robustness on bumped devices","authors":"Jayson Rae Tulas, Tony Taloban","doi":"10.1109/EPTC.2015.7412341","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412341","url":null,"abstract":"The substrate design chosen for the newer Silicon (Si) node utilizes a low core thickness compared to previous Si nodes which used a high core thickness substrate. One motivation to move to low core thickness is the better electrical performance it could provide to the package, especially since most of the newer silicon technology devices are used for high powered applications. A low core substrate offers shorter routing for the current which minimizes the losses incurred during the travel of current from ball to die and vice versa. While it is better in terms of electrical performance, a low core thickness substrate presents new challenges in terms of manufacturability and reliability. Bump cracks and pad cracks were observed on the initial reliability tests. As such, the team collaborated with substrates suppliers to provide a solution that will make the newer silicon technology packages robust enough to withstand the adverse effects of package warpage, stress and solder voids. Microball (uBall), which is a new bumping technology and thicker Copper (Cu) pad are among the improvements in this paper. This paper also documents the root cause analysis, evaluations and verifications done to validate the effectiveness of identified corrective actions.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126112601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Study on power cycling reliability of power module with single metal layer flexible substrate by finite element analysis","authors":"Zhaohui Chen, How Yuan Hwang, N. Jaafar, D. Rhee","doi":"10.1109/EPTC.2015.7412307","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412307","url":null,"abstract":"In this paper, the power cycling simulation model was built up to study the thermo-mechanical reliability of the power electronic package test vehicle with single metal layer flexible substrate. The power cycling simulation includes thermal analysis and thermo-mechanical analysis. The temperature distribution of the high power electronic package was obtained by the thermal analysis. The stress and strain behaviors of the die attach materials and Al bonding wires of the power electronic package were investigated by the coupled thermo-mechanical simulation. The fatigue lives of the die attach materials and Al bonding wires were estimated by the plastic-strain based Coffin-Manson fatigue life prediction model. The effects of the die materials, epoxy molding compound (EMC) and die attach materials were also investigated by the parametric studies with the numerical simulation results.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"101 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120886387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ziyu Liu, Qian Wang, Jian Cai, G. Zou, Lei Liu, Daozhi Shen, Lin Tan
{"title":"Cu-Cu bonding by Ag nanostructure at low temperature of 180 °C","authors":"Ziyu Liu, Qian Wang, Jian Cai, G. Zou, Lei Liu, Daozhi Shen, Lin Tan","doi":"10.1109/EPTC.2015.7412274","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412274","url":null,"abstract":"In order to lower Cu-Cu bonding temperature and shorten bonding time applied for 3D integration, nanostructure has been introduced on bonding Cu surface. However, few studies have been reported on Nano Particles (NPs) formation by film deposition process such as pulsed laser deposition (PLD), which would be compatible with CMOS process. In this work Ag nanostructure containing strings of NPs was formed by optimized PLD process, which is mostly used for nanofilm deposition. Then NPs morphology was observed by scanning electron microscope (SEM) and transmission electron microscopy (TEM). Ag nanostructure was consisted of strings of loose mesh structures filled with NPs with size range from several nanometers to tens of nanometers. They were compressible and of high movability, which was significantly benefit for lowering bonding temperature. With these Ag nanostructure on Cu pads, chips were pre-bonding at the low temperature of 180°C for 5 min and afterwards all the chips were simultaneously annealed at the temperature of 200 C for 25 min. After die shear test, average shear strength of 15.8 MPa was obtained and fracture surface was inspected by SEM. After TEM observation of bonding interface, continuous Cu-Ag-Cu interfaces with almost no void were observed. It confirmed low temperature Cu-Cu bonding with Ag nanostructure by PLD was a reliable and time-saving process, which might be a promising technology for 3D integration.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121334762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Study the oxidation resistance on palladium-coated Free Air Ball","authors":"L. Tang, Yue-Jia Zhang","doi":"10.1109/EPTC.2015.7412413","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412413","url":null,"abstract":"The use of Palladium-coated Copper (Pd-Cu) wire helps prevent Copper (Cu) oxidation before and during the bonding process. Different EFO current, firing time and ball size ratio (BSR), affect the roundness of the Free Air Balls (FABs) formed and the distribution of Pd on the surface of the FABs. In this paper, Pd-Cu wires of diameter 0.8 mil were used and 3 settings of Electronic Flame Off (EFO) current and firing time were used. Optical and scanning electron microscope (SEM) inspection were used to observe the shape of the FABs formed. Energy-dispersive X-ray spectroscopy (SEM-EDX) was carried out to observe the Pd distribution as well as the oxidation condition on the surface of the FABs. Other than the optical and SEM inspections, Focused Ion Beam (FIB) and Transmission electron microcopy (TEM) were carried out after a Pressure Cooker Test (PCT) to further investigate the corrosion phenomenon of Cu on FAB surfaces. It was found that for FAB surfaces which contain Pd, even if there is not complete coverage of Pd, the Cu oxidation is a slow process and that FABs with higher Pd content have better corrosion resistance performance. Cu Grain boundaries show the weakest location for corrosion resistance in the FAB.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121339363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Li, Norhanani Binte Jaafar, M. I. E. Sam, Kalyn Lim Tien Shee, Wong Lai Yin, Chui King Jien
{"title":"Study of barrier layer thickness effect for the micro-bump","authors":"H. Li, Norhanani Binte Jaafar, M. I. E. Sam, Kalyn Lim Tien Shee, Wong Lai Yin, Chui King Jien","doi":"10.1109/EPTC.2015.7412328","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412328","url":null,"abstract":"With the semiconductor development, more and more different devices need be integrated to achieve faster and more functionalities. Micro-bump is an important connection from chip to chip, chip to wafer and chip to substrate. We evaluated micro-bump barrier layer Ti thicknesses (400Å, 1KÅ and 2KÅ) effect on shear strength and bump chain resistance in this study.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126748147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A study balancing physical properties for an optimized thermal interface material","authors":"L. Larson, Xiao Dong Wang, Yin Tang, A. Zambova","doi":"10.1109/EPTC.2015.7412273","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412273","url":null,"abstract":"Thermal dissipation requirements for advanced flip chip devices are becoming significant. High end flip chip devices that used lidded packages are now being redesigned to utilize even more advanced materials. Devices that previously did not require a lidded package are now being forced to utilize such a package. The latter scenario can also can benefit from more advanced materials. Initial thermal performance is a key factor for selecting a candidate thermal interface material (TIM), but how well the package can survive reliability conditions is also important. Cost pressures on the overall structural design can also be a significant factor for some types of applications. Polymeric TIMs can address many of these issues by having a high initial thermal performance and by allowing adequate mechanical stress relief to survive reliability conditions. The TIM properties, such as elongation and modulus can be as important as the thermal conductivity. Properties such as thermal resistance and thermal impedance are even more important. This paper will detail how these properties are inter-related and will demonstrate that an optimum balance between them can be achieved.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121519203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}