2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)最新文献

{"title":"Chip to chip interconnection for system in packaging using Cu stud bump","authors":"K. Muniandy, N. Khan, Foong Chee Seng, C. Lo, Lim Meng Rong","doi":"10.1109/EPTC.2015.7412297","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412297","url":null,"abstract":"The current market trend for chip on chip connection is mainly using copper pillar. The copper pillar technology has been around for many years and advances in the copper pillar technology have grown steadily over the past few years. The main issue with copper pillar is the cost. Bumping a single piece of 12 inch wafer will cost approximately above USD100 - 200. The alternative low cost method studied in this paper is by utilizing copper stud bumps with the combination of anisotropic conductive adhesives to create the inter-metallic connection between the top die and the bottom die.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121871222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Forced-time controlled transient dynamic wire bonding simulation for wire bond process development","authors":"C. Meng, Eric Yik","doi":"10.1109/EPTC.2015.7412397","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412397","url":null,"abstract":"In wire bond process, wire bond recipe is predefined to wire bonder before the start of wire bonding. This wire bond recipe comprises of single step to multi steps bond force and ultrasonic control depending on type of wire material and bond pad technology to use in wire bonding program [1]. The program always start with wire bondability assessment by manipulate different bond force, ultrasonic power and time to achieve good and reliable bond quality. However, it is not always well understood the fundamental of wire bond mechanism and furthermore it is challenging to quantify the wire bond mechanism with existing measurement equipment and techniques [2]. Hence, numerical simulation technique is still the best tool to re-analyze the wire bond process mechanism and subsequently by using reverse engineering approach to understand and re-evaluate wire bond mechanism. This paper presents an alternative analytic method by using explicit simulation technique with stress sensor correlation to investigate the effect of wire bond recipe to dynamic stress on smashed FAB and bond pad structure during touch down and ultrasonic bonding process. Force-time controlled transient explicit simulation technique was used to define the wire bond recipe and correlated with stress sensor measurement results. ANSYS Ls-dyna explicit simulation software was used in the simulation prediction and stress sensor chip was used to measure stress induced in wire bond process. The results were correlated and used for subsequent wire bond assessment. Preliminary results show simulation prediction has successfully predicted the initial touch down impact on bond pad and the stress distribution and evolution throughout the change of bond force profile. This important information provide valuable understand of wire bond touch down impact and ultrasonic characteristic in wire bond process.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114965027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Effects of solder alloy compositions on microstructure and reliability of die-attach solder joints for automotive applications","authors":"Weiping Liu, N. Lee, P. Bachorik, C. Labarbera","doi":"10.1109/EPTC.2015.7412359","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412359","url":null,"abstract":"For harsh electronics environments, where some applications (e.g., automotive and defense) require operating temperatures at 150 °C or higher, the Pb-free SnAgCu (SAC) solders such as Sn3.0Ag0.5Cu (SAC305) and Sn3.8Ag0.7Cu (SAC387) alloys are not reliable enough to replace the high-Pb, high melting temperature solders. Harsh environment electronic industries that are currently exempted from RoHS regulations are actively searching for a suitable replacement solder. In this study, new Pb-free solder alloys based on SnAgCuSbBi with variations of Sb, Bi, and Cu alloying contents and Ni/Co dopants were tested against the conventional high-Pb solder (92.5Pb5Sn2.5Ag) in an effort to meet the requirements for the harsh environment electronics applications. Evaluations were conducted on Si die-attach assemblies on Ni-plated Cu lead-frame made with solder preforms in thermal shock cycling tests (-40°C to 150°C with a dwell time of 20 minutes). Crack length measurements in the solder joints and die shear strength tests were performed after various cycles of the thermal shock testing. The solder joint microstructures and effects of alloy compositions were also investigated by means of optical and scanning electron microscopy coupled with energy dispersive X-ray spectroscopy (EDS). The results show that the solder alloys compositions significantly influence the microstructure and reliability of die-attach solder joints. The novel Pb-free solder alloys based on SnAgCuSbBi outperform the high-Pb high-temperature solder in the reliability testing.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127677059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High volume EMI-shielding process for LGA and BGA components","authors":"J. Pettit, A. Law, A. Brewer, J. Moore","doi":"10.1109/EPTC.2015.7412379","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412379","url":null,"abstract":"Electro Magnetic and Radio Frequency Interference (EMI/RFI) occur in mobile electronics as high functioning devices with multiple operating frequencies are packaged in dense form factors. The most fundamental protection is through metal shielding to produce a \"Faraday Cage\" (e.g. a metal box) [1], a structure that absorbs or reflects EMI/RFI and boosts performance. A simple and direct means to shield packages is through physical vapor deposition (PVD). Temporary bonding adhesives are used to affix land grid array (LGA) and ball grid array (BGA) packages onto substrates and sent into the PVD line. The properties of the adhesive must be thermally stable, exhibit reduced sidewall creep, prevent under-side deposition (back spill), and be free of residue. Several adhesive solutions exist for EMI shielding processes [2], they exhibit low outgas to 300°C, and are proven to accept package bow and warp of greater than 30um [3]. LGA and BGA packages are affixed using a sufficient adhesion force that is tuned by mixing different resin molecular weights (MW) and activator amounts, all known to have a direct effect on peel force. Adhesion force has been shown to trend with MW of the resin and seemingly supports affixing, while simultaneous adjusting down activator until tearing begins to produce unwanted residue (Fig. 3). Through tuning, solutions are created that allow rapid sealing of small components with topographies exceeding 300um, metal deposition, and rapid satisfactory removal. These temporary bonding adhesives are formulated to achieve a desired modulus and elasticity to accept small packages, allow rapid processing and support high volume manufacturing. Similar work has been conducted to reduce the bow/warp of interposers during stacking with micro-bumped chips. The C4 bumps are encapsulated and protected during thermal exposure [4]. Simple tapes may support low profile LGAs whereas the high standoff in BGAs can create challenges in proper affixing, sealing, and processing. One solution in affixing packages with topographies is based upon the use of rigid etched or \"pocket\" carriers [5]. Once believed to be a solution for high-density placement of BGAs, there exist challenges in geometric design, glue placement, execution, and recycling (cleanup). Another possible solution is tape that is patterned using CAD-driven laser tooling, producing pockets within the flexible backing. However, the same flexible plastic backing that provides simplicity and ease creates challenges during high-density placement. Placement on flexible tapes can shift to lower density (increased separation), reduction in throughput, and increased cost of ownership (COO). New affixing introductions include laminates and composites that combine the design targets of rigid carriers with the simplicity of tapes [2]. While activity in affixing technologies remains high, PVD systems are also shifting towards small footprints and lower operating temperatures. While low temperatures may","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121381773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Influence of acid copper plating additives on void formation during high temperature storage","authors":"Ronizan bin Mohd Salleh, Lai Chin Yung","doi":"10.1109/EPTC.2015.7412410","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412410","url":null,"abstract":"Formation of voids at the interface between Cu/Cu3Sn or within Cu3Sn phase can be observed when Sn plated on electrolytic copper surface is subjected to High Temperature Storage of 150°C for 1000 hours. In this study, acid copper plating system consists of organic additives was used for the copper plating process. Without copper plating additives brightener and leveller, minimum voids were distributed uniformly at Cu3Sn phase. Addition of SPS or brightener to the system without leveller or PEG showed the density of voids became more and distributed along the Cu/Cu3Sn interface. However, when leveller been introduced to the system containing the brightener, the cross section showed the voids were reduced and uniformly distributed along the Cu3Sn layer.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122566232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electrically conductive adhesives for demanding temperature cycling environment with water immersions","authors":"S. Lahokallio, J. Kiilunen, L. Frisk","doi":"10.1109/EPTC.2015.7412362","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412362","url":null,"abstract":"Electrically conductive adhesives are versatile attachment materials offering benefits for many applications in industrial electronics. However, the stability of these materials is typically less than that of metals and ceramics, thus their suitability for demanding environments must be carefully studied. In this paper the performance of anisotropically conductive adhesive (ACA) attachments was studied in a demanding environment combining both high temperature cycling and water immersions. Real-time measurements were conducted during testing. Significant differences between the ACA materials were seen. Promising results were obtained with some of the ACA materials studied, emphasising the importance of material choice. Cracking in the ACA interconnections could be seen in some of the samples studied for failure analysis. However, it remained unclear whether the cracks were the reason for the failures during testing.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116138127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"eWLB and the challenge of metal burr at die edges","authors":"Eoin O'Toole, J. Campos, S. Kroehnert","doi":"10.1109/EPTC.2015.7412353","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412353","url":null,"abstract":"Embedded Wafer Level Ball Grid Array (eWLB) [1] since it's invention has been the leading technology for Fan-Out Wafer-Level package. The development of eWLB technology involving the patterning of a Redistribution Layer over a reconstituted wafer has been hampered by remaining metal from the test structures applied by the foundries in the dicing streets of the incoming Si wafers for process control. Depending upon the functionality of the product and the foundry technology being applied the materials employed both for metallization and passivation vary considerably. For the vast majority of applications the last metal continues to be aluminium with or without copper and silicon dopants. The thickness of the aluminium varies from ~1 μm to ~10μm. When traditional blade dicing is used to dice through these structures the aluminium curls up to form a metal burr ranging in height from a few microns to tens of microns. When the re-passivation dielectric is applied to the reconstituted wafer with those dies embedded using a typical spin coating process, depending upon the dielectric, it becomes difficult to guarantee that an effective coverage of the metal burr is achieved. The consequence of electrical contact between the metal burr and the redistribution layer formed on top of the dielectric can be innocuous with no detrimental impact in terms of device performance. If the position of the metal burr coincides with the position of two or more metal traces a short circuit can be formed between the traces often representing a significant yield loss impact. In this paper a number of solutions to this problem which have been developed by NANIUM will be presented. The basis of these solutions may be broken down into three main categories, optimized and adaptive blade dicing, laser grooving, and an innovative chemical wet etch process. Results will be presented for all of the techniques described with benefits and limitations explained in detail.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127418535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Conformable body patches for ultrasound applications","authors":"Shivani Joshi, Sourush Yazadi, V. Henneken, R. Dekker, Renee Sanders","doi":"10.1109/EPTC.2015.7412278","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412278","url":null,"abstract":"There is a growing interest for the application of CMUT ultrasound transducers in applications other than traditional diagnostic imaging. Many of them require large area ultrasound transducers which need to be in close contact with parts of the body. Depending on the body area, these transducers therefore need to have some degree of stretchability in order to conform to the curvature of the human body. For the fabrication of these stretchable transducers, the total transducer is sub divided into separate small rigid tiles that are electrically interconnected, and embedded in a stretchable polymer. The EPlaR release process offers an industrial manufacturing platform for these devices.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127432677","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The impact of high glass transition temperature of molding compounds on power package warpage and stress performance","authors":"Dandong Ge, N. Subramanian, Khai Seen Yong, M. Y. Foo, S. L. Gan","doi":"10.1109/EPTC.2015.7412356","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412356","url":null,"abstract":"High Glass Transition Temperature (Tg) Molding Compound (MCs) are preferred for power and automotive packages due to their suitability in high temperature applications. However, our recent study on high Tg MCs showed that their susceptibility for delamination risk increased especially at low temperature conditions. In this work, three types of Mold Compounds were intentionally selected for evaluation and comparison. There are two High Tg MCs and one normal Tg MC with multi-aromatic resin. Properties of MC samples, mainly their weight loss, Tg, CTE and Storage Modulus, were measured and recorded by means of TGA, Thermal Mechanical Analysis(TMA) and Dynamical Mechanical Analysis(DMA). TMA and DMA were used to characterise the viscoelastic behaviour of 3MCs over temperature. In this study, we evaluated with finite element analysis (FEA) the impact of mold compound on chip deformation and induced stresses at bi-material interfaces within the package for qualitative correlation & risk assessment of chip crack & interfacial delamination during assembly process steps & thermal cycling (TC) reliability test temperatures.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127325489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Process and challenges of ultra-thick spin-on photoresist","authors":"S. W. Ho, S. A. Sek, B. L. Lau, V. S. Rao, T. Chai","doi":"10.1109/EPTC.2015.7412365","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412365","url":null,"abstract":"In this paper, spin-on photoresists were evaluated to form ultra-thick photoresist mold for electroforming of 200 μm height Cu pillar structures with a diameter of 150 μm. Two photoresists materials of different exposure tone (positive & negative) were assessed. A double spin-coating process was required to achieve the required resist film thickness. The soft-bake, exposure and developing parameters were optimized to obtain suitable photoresist profile. Substrates with developed photoresists were subjected to electroplating process to test their chemical resistance A stepped EBR was implemented to overcome poor electrical contact with plating jig due to the thick edge bead. After Cu electroplating, the different materials were subjected to stripping solvent to assess their stripping performance.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131904458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}