eWLB and the challenge of metal burr at die edges

Abstract

Embedded Wafer Level Ball Grid Array (eWLB) [1] since it's invention has been the leading technology for Fan-Out Wafer-Level package. The development of eWLB technology involving the patterning of a Redistribution Layer over a reconstituted wafer has been hampered by remaining metal from the test structures applied by the foundries in the dicing streets of the incoming Si wafers for process control. Depending upon the functionality of the product and the foundry technology being applied the materials employed both for metallization and passivation vary considerably. For the vast majority of applications the last metal continues to be aluminium with or without copper and silicon dopants. The thickness of the aluminium varies from ~1 μm to ~10μm. When traditional blade dicing is used to dice through these structures the aluminium curls up to form a metal burr ranging in height from a few microns to tens of microns. When the re-passivation dielectric is applied to the reconstituted wafer with those dies embedded using a typical spin coating process, depending upon the dielectric, it becomes difficult to guarantee that an effective coverage of the metal burr is achieved. The consequence of electrical contact between the metal burr and the redistribution layer formed on top of the dielectric can be innocuous with no detrimental impact in terms of device performance. If the position of the metal burr coincides with the position of two or more metal traces a short circuit can be formed between the traces often representing a significant yield loss impact. In this paper a number of solutions to this problem which have been developed by NANIUM will be presented. The basis of these solutions may be broken down into three main categories, optimized and adaptive blade dicing, laser grooving, and an innovative chemical wet etch process. Results will be presented for all of the techniques described with benefits and limitations explained in detail.