2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)最新文献

{"title":"Band widening technique for small integrated packaged antennas","authors":"M. Rotaru, J. Sykulski","doi":"10.1109/EPTC.2015.7412406","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412406","url":null,"abstract":"In this work a different approach to widen the bandwidth of an electrically small antenna is proposed. Unlike other methods reported in literature the idea explored here uses the feeding network to improve the bandwidth. The methodology is illustrated using a circular patch antenna for testing purposes, but there is no fundamental reason why this approach would not work for other types of antenna. All presented results were obtained from full wave simulations of the antenna structure using commercial software.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128198991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Insulated Au-Flash PdCu wire processing and wire bond process robustness improvements for TBGA & LQFP packages","authors":"S. C. Teck, E. P. Leng, T. Chu, M. R. Ibrahim, Zhang Xi, Loh Wan Yee, Su Dan, T. C. Wei","doi":"10.1109/EPTC.2015.7412412","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412412","url":null,"abstract":"The insulated Au-Flash PdCu wire (X-PdFLASH) study was first initiated by Freescale, Heraeus and Microbonds with the insulated technology from Microbonds since one year ago. Since then, continuous improvements in the wire processing was conducted by machine hardware modification, process parameter re-optimization to attain a more homogeneous insulation coating layer. This was confirmed by the improved distribution of the Break-Down-Voltage (BDV) measurement as homogeneous insulation coating layer is the most critical aspect of the insulation wire quality and performance. The improvement was further verified on the wire bonding responses with the Freescale TBGA package with significant improvement on the Stitch Pull Strength, MTBA and Floor Life as compared to the original wire condition. Meanwhile under the original wire condition, the 0.8mil X-PdFLASH wire was also bonded on Freescale LQFP package. The inherent LQFP package design causes high-sensitivity to 2nd bond short-tailings due to clamping instability especially on the ground bonds. Many potential optimizing areas were assessed to improve the 2nd bond bondability. Among them were capillary geometry type and design; the wire bonder P-Parts design to improve the clamping and 2nd bond process enhancements which includes Stand-Off-Stitch-Bond(SSB). All of which still does not provide a robust bonding process and minimum stitch value also falls below the specifications. By adopting of the newly improved wire process from 0.7mil wire, the 2nd bond bonding process of 0.8mil X-PdFLASH is still unsatisfactory in terms of stitch pull value and stitch bond shape. Finally, the newly-developed 2nd bond bonding process from K&S, the Pro-Stitch-Plus (PSP) was evaluated together with the improved 0.8mil wire on the LQFP package. Encouraging bonding results were achieved by a stable bonding process, good stitch bond shape and stitch pull values within the specifications. The initial UPH assessment also showed a significant improvement. In summary, the further wire manufacturing process & equipment improvements substantially improve the overall wire coating consistency and thus enable a better HVM wire bond performance. Besides, the joint development work of Heraeus - Freescale - Micorbonds which successfully established an optimized wire bond recipe for LQFP package through a detailed process characterization indicates another great leap in the insulated wire bond application.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115393060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Characterization of pressure-less Ag sintering on Ni/Au surface","authors":"Lee Jong Bum, A. Li, How Yuan Hwang, Pan Wei Chih, Y. Xin, Rhee Min Woo Daniel","doi":"10.1109/EPTC.2015.7412369","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412369","url":null,"abstract":"Ag sintering has been widely studied as a lead-free die attach solution for power electronics. A soak time of a dozen minutes at the sintering temperature is necessary to establish strong bond strength by the conventional heating method. Chemical bonding can be achieved by various parameters associated with the metallurgical bond of the adjacent surfaces. In this study, attaching technology between Au coated Si die and Au coated Si substrate was developed by applying Ag sintering materials which can work at temperature up to 350°C. It was concentrated on finding so called \"pressure-less sintering and pressure sintering\" procedure in air and N2 environment. The sintering was performed in air or N2 at temperature range from 180°C to 280°C for 10 minutes to 3 hours. Highest shear strength was obtained at 200°C of sintering temperature bonded for 3 hours.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117122254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electrical transmission characteristics of differential TSV structures in 3D TSV packaging","authors":"Meng Zhen, Yan Yue-peng, Wang Chen, Zhang Xingcheng, Liu Mou","doi":"10.1109/EPTC.2015.7412269","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412269","url":null,"abstract":"The electrical characteristics of Through Silicon Via (TSV) have been frequently studied recently, but most studies focused on the single-ended TSV structure. Specially, study about the differential TSV structure is rather limited. In this study, three-dimensional electromagnetic simulation software HFSS was used to analyze the transmission characteristics of the differential signal of the differential TSV structure. Firstly, the differential TSV structure was modeled to analyze the impact on the transmission characteristics of differential signal by the main structural parameters achieved in the mainstream process. Our results indicate that the forward transmission gain increases when the TSV diameter and the thickness of the SiO2 oxide isolation layer increase. However, the forward transmission gain decreases when the TSV height increases. Secondly, the differential TSV structure in the TSV arrangement was modeled. The influence of the pitch of the differential TSV pair on the transmission performance of the differential signal is not a one-way process. Finally, the conical differential TSV structure was modeled to study the influence of non-ideal cylinder shape on the transmission performance of the differential signal. Our results indicate that the forward transmission gain increases when the upper diameter increases and the bottom diameter keeps unchanged.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124891473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Temperature cycling of low voltage motor drives","authors":"J. Pippola, J. Kiilunen, L. Frisk","doi":"10.1109/EPTC.2015.7412376","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412376","url":null,"abstract":"Motor drives are used in a wide range of industrial applications, many of which impose high reliability demands on the electronics used in them. Moreover, the environmental conditions in industrial applications may vary a lot and therefore reliability studies for the motor drives are essential. In this study the reliability of a low voltage motor drive was studied with two different temperature cycling profiles. The results of the study showed that temperature cycling triggered some reversible device faults during testing, but catastrophic IGBT failures, common for power electronics, were less seen. More detailed analysis suggests that the reason for the device faults may have been cracks in the solder joints of the pinheader connector between two PCBs of the device, or fretting corrosion on the connector contact materials.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116218029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of fluxless flip chip reflow process for high density flip chip interconnect","authors":"S. Lim, M. Ding, Jong-Kai Lin, V. S. Rao","doi":"10.1109/EPTC.2015.7412342","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412342","url":null,"abstract":"In flip chip technology, flux is widely used to clean the surface of the solder bumps and the surfaces to be soldered for good wetting of the solder bumps on the conductive bond pads [1]. Moreover, flux helps to keep the flipped chip in position and hold it during die placement and the subsequent reflow process. However, this flux-containing reflow can cause problems and inconveniences. For example, volatile materials are generated when organic fluxes decompose during heating. These volatiles could be trapped in the molten solder and form voids, which degrade mechanical and electrical properties of the solder joints, and affect the subsequent chip bonding process [2]. In addition, flux residues adversely affect underfill interfacial adhesion in the flip chip assembly process. Flux residues must therefore be removed, which is typically done through post-reflow cleaning. With no-clean fluxes, which include a small amount of activators to minimize residues, there is a tradeoff between reduced residues and diminished flux performance. Because of the problems associated with organic fluxes, there is a need to study the fluxless solder reflow process [3]. In this paper, we study the fluxless flip chip reflow process and evaluated the reliability performance for 2 different test dies onto the 100um thin 2.5D TSV Si interposer using a temporary adhesive material. The assembled sample is then subjected to a lead-free reflow profile in vacuum oven with forming acid. One advantage of the temporary adhesive material is that it will evaporate at reflow temperature. Results showed that both test dies passed moisture sensitivity level test level 3 under Jedec standard J-STD-020 (30°C/60%RH) for 192 hours without any underfill delamination.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122518890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of Al and Ge surfaces for Al-Ge wafer level eutectic bonding","authors":"G. Chua, Bangtao Chen, Navab Singh","doi":"10.1109/EPTC.2015.7412394","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412394","url":null,"abstract":"Metal based wafer level eutectic bonding has been developed for hermetic sealing providing consistent gas environment for MEMS Silicon (Si) sensor devices as well as protecting the MEMS structure. The use of Aluminum (Al) and Germanium (Ge) materials for bonding has advantages as these materials are CMOS compatible with Al conventionally used for wire bonding and metal pads, and Ge for creating SiGe CMOS devices. Al-Ge bonding is also comparatively low cost compared to gold and silicon (Au-Si) bonding. For successful eutectic mixture during bonding process, the two metal surfaces on both sides of the wafers to be bonded have to be cleaned and cleared of native oxides and contaminants. This work examines the Al and Ge surfaces prior to bonding that affects the formation of Al-Ge eutectic reaction.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122847594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Assessment on palladium-coated copper wire bonding for 28nm Cu/low-k chips: Al bond pad and NiPd bond pad","authors":"L. Wai, Dhayalan Mariyappan, C. G. Koh, T. Chai","doi":"10.1109/EPTC.2015.7412301","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412301","url":null,"abstract":"In this study, palladium coated copper core wire is evaluated and a series of bond quality test is carried out on Aluminum (1.5μm Al) bond pad and Nickel Palladium (2.5μm Ni/0.3μmPd) bond pad with Ø0.6mil palladium-coated copper core wire. From the optimization with mechanical chips, it is found that NiPd has larger bond parameters windows than Al bond pad. Ball shear strength of NiPd samples becomes higher after 175°C high temperature aging test for 1K hours. Al bond pad samples have some pad peel with shear strength >8 gf/mil2 after 1K hours aging at 175°C. Cu/low-k chips with 1.5μm thick Al bond pad bonded with 0.6mil palladium-coated copper wires are ball sheared and wire pulled at time zero and after 96 hours aging test, and it passes ball shear and wire pull test. It is observed that NiPd follows the contour of Al surface during the plating on Cu/low-k chip with Al bond pad, and plating scenario applies for Al bond pad with large probe mark. There is no gap being observed in between the bonded ball and NiPd bond pad even though there is a large probe mark. NiPd pad does not form intermetallic after aging test when compare to Al bond pad sample which has Cu-Al intermetallic being found after aging for long hours. NiPd bond pad provides excellent shielding for Cu/low-k structure where there is no deformation of the bond pad after bonded with palladium-coated copper core wire.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114285220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High-speed optical three dimensional measurement method for micro bump inspection in 3D LSI chip stacking technology","authors":"M. Aoyagi, N. Watanabe, K. Kikuchi, S. Nemoto, Noriaki Arima, M. Ishizuka, Koji Suzuki, Toshio Shiomi","doi":"10.1109/EPTC.2015.7412405","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412405","url":null,"abstract":"3D LSI chip stacking technology has been developed in AIST using cone shape micro bumps fabricated by nanoparticle deposition method. The cone shape bumps are suitable for a thermocompression bump joint process with low temperature and low load force, where the bumps are easy to collapse with loading due to the pointed structure. High yield micro bump joints can be obtained. The three dimensional measurement of the cone shape bumps can be done using laser scanning microscope or scanning electron beam microscope. It is not suitable for a mass production inspection test. We have proposed a new optical three dimensional structure measurement technique using optical microscopes with image sensors or line sensors. We developed recently a high-speed optical three dimensional measurement system using specially manufactured optical microscopes with high-speed 8192-pixel line sensors, which can be used for a mass-production process line. Blue laser diffused illumination was equipped to obtain a high resolution. The cone shape bump height measurement with standard deviation less than 0.3 μm was confirmed. The high-speed wafer measurement was demonstrated using 10 μm diameter Cu pillar bumps.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114380133","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of high reliability lead-free solder joint dispersed IMC pillar","authors":"Y. Hayashi, I. Shohji, Yusuke Nakata, Tomihito Hashimoto","doi":"10.1109/EPTC.2015.7412284","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412284","url":null,"abstract":"The aim of this study is to create a high reliability solder joint for automotive applications by actively utilizing IMC formation in the joint. The method to disperse pillar-shaped IMCs in the solder joint with Cu was examined with four types of lead-free solder. In the joint with Sn-0.7Cu-0.05Ni (mass%), growth of pillar shaped (Cu, Ni)6Sn5 IMCs which connect Cu plates on both sides was observed when bonding was conducted at 300°C for 30 min. In the joint with Sn-3.0Ag-0.7Cu-5.0In (mass%), coarsen columnar CueSn5 IMCs which include a few mol % In grow in relatively random directions in bonding at 300°C for 30 min. The growth rate of IMCs in bonding is the largest among solder investigated. In the joint with Sn-5.0Sb (mass%), thick columnar CueSn5 IMCs grow from both Cu sides although there are no IMCs to connect Cu plates on both sides in bonding at 300°C for 30 min. For joints with Sn-3.0Ag-0.7Cu-5.0In and Sn-5.0Sb, an effectively IMC dispersed joint is expected to be fabricated by optimization of bonding conditions. In the joint with Sn-3.0Ag-0.5Cu (mass%), a thick scallop shaped IMC layer forms at the joint interface and thus it is difficult to fabricate pillar shaped IMCs to connect Cu plates on both sides.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129601666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}