2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)最新文献

{"title":"Developments of FIWLP/WLCSP technology based on Enhanced Dielectric Material and optimized design options","authors":"J. Campos, Vitor Chatinho","doi":"10.1109/EPTC.2015.7412329","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412329","url":null,"abstract":"WLP has been a gradually adopted by the industry during the last years due to its unique characteristics regarding package size and height, package electrical and thermal characteristics and cost. As one of the earlier formats of this wafer level packaging technology, FIWLP is actually its main version with several WLCSP products in HVM since several years, and being adopted in more and more mobile devices. NANIUM, S.A, as a major WLP assembly and test services provider, has been gradually enlarging its WLP capabilities also for FIWLP / WLCSP products. With its recent introduction of an \"Enhanced Dielectric Material for improved reliability performance\" (ref. ECTC2014 [9]) for its FOWLP/eWLB technology and following qualification also for FIWLP/WLCSP, NANIUM demonstrated a superior package and board level performance on all its WLP technologies. This paper will describe the different developments that have been carried for FIWLP/WLCSP technology regarding BLR and cost reduction. Several examples of different test vehicles designed and tested to demonstrate such developments will be reviewed like comparisons between 3Mask and 4 Mask process; between 0.4mm and 0.35mm bump pitch, and other design/process/material variations. Finally this paper will also share an outline of actual and future developments and paths regarding simplification of its process flow; reduction of its BOM cost and improvement of its quality and yield.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130540569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Heat transfer enhancement factor characteristics for collective cooling using inclined air jet","authors":"S. Ingole, K. Sundaram","doi":"10.1109/EPTC.2015.7412395","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412395","url":null,"abstract":"The inclined jet of air is experimentally investigated with the aim of understanding thermal characteristics for cooling applications which can be used in electronics packaging applications. Entire study and evaluations are made by insertion of jet on the leading edge of a horizontal rectangular hot target plate. The jet is placed at height H from target to be cooled, and investigated for downhill side collective cooling performance approach. The experiments are performed at jet Reynolds number in the range of 2000 ≤ Re ≤ 20000 with circular jet and inclination of 15° to 75°. The heat transfer Enhancement Factor (EF) is defined and analyzed on the basis with natural convection. The equations for maximum and minimum EF are developed imperially which is the function of Reynolds number, jet inclination, target to jet height, and jet diameter. It is experimentally observed that average EF is highest for 6a of 45°. The 60° and 75°jet inclination follows nearly similar trend, but at lower side; and 30° and 15° gives the lowest average EF. At high Reynolds number up to 20000, improved cooling performance is seen. It is followed by Reynolds number of 16000. At lesser Reynolds number, jet continuously gets attached to target plate, whereas at moderate Reynolds Number up to 20000, the flow jump is observed by which, it creates waves in flow. Evidently thermal characteristic also depends on height between target surfaces to jet. The physics of inclined flow is analyzed taking samples of three major important inclinations below 90 degree. The effect of jet to target distance (H) is also investigated in the range 0.5 ≤ H/D ≤ 6.8.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123599015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A comparative study of the relative performances of the sinter-silver die attach materials","authors":"Q. Qi","doi":"10.1109/EPTC.2015.7412418","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412418","url":null,"abstract":"Die attach materials play an important role in meeting the demanding thermal management requirements of high power devices. Conventionally, silver filled conductive epoxy materials provide low cost solutions and Au-Sn soldering solution meet the higher power application needs. While epoxy based die attach materials have seen widespread use and continued performance improvement over years, contact thermal resistance at the interface often presents a challenge to achieving the claimed thermal performance of the bulk materials; on the other hand, soldering die attach requires higher reflow temperature than many applications can endure and, in some cases, soldering die attach performance is still insufficient to meet the ever-demanding high power applications. In addition, the leading Pb-free soldering die attach, Au-Sn, is costly and should be replaced if possible. There have been significant development of sinter-silver (S-Ag) die attach solutions in recently years. Several materials vendors announced new product offerings with different claims of performances. It is with this in mind that we present a study of the relative performances of several S-Ag die attach materials using a standard QFN package to: 1. Quantify the relative thermal performances of different S-Ag die attach materials 2. Benchmark the results against Ag-filled epoxy die attach 3. Benchmark the results against pressure-assisted S-Ag die attach 4. Assess the relative reliability performance with accelerated stress tests 5. Perform F/A analysis to understand the failure mode of the S-Ag die attaches To remove ambiguity of the thermal measurement results, a CMOS thermal test die with uniform heaters and sensitive junction temperature detection diodes is assembled onto a QFN lead frame with S-Ag die attach materials from different vendors, along with some Ag-filled epoxy and a pressure sinter-Ag die attach materials. To ensure accuracy of the thermal measurements; a transient thermal measurement method based on Mentor Graphics' t3Tster test system was used, which allows capture of the die attach thermal resistance and the identification of the thermal conductivities of the S-Ag die attach. The obtained results are benchmarked against known materials properties and compared with vendor's datasheet. To help assess the relative reliability and thermal stabilities of these die attach materials, the assembled QFN's were subjected to MSL3 pre-conditioning and accelerated thermal cycling test (ACT) between -55 to 125C and then thermally measured again. Comparisons between the initial and post-stress thermal measurement results provide insight and help understand any potential thermal performance change as well as reliability implications. This is the first systematical study of its kind to give a side-by-side comparison of the performance of different S-Ag die attach materials.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114211541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Wafer level CSP with ultra-high thermal reliability lead-free alloys","authors":"M. Ribas, G. Lim, Rommel T. Bumagat, Anilesh Kumar, Divya Kosuri, Prathap Augustine, P. Choudhury, R. Rangaraju, S. Telu, S. Sarkar, M. Sobczak, Bawa Singh","doi":"10.1109/EPTC.2015.7412266","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412266","url":null,"abstract":"Wafer-Level Chip-Scale Packaging (WLCSP) has become increasingly popular in portable electronics. One of its main characteristics is its reduced scale and that the solder balls are attached directly to the device. One of the main challenges in WLCSP is how to overcome the effects of thermal mismatch between the silicon die and the printed circuit board that arise from these characteristics. Use of new solder alloys is one of the ways to mitigate thermal fatigue stresses resulting from coefficients of thermal expansion mismatch. Tensile tests and high temperature creep tests were used for initial screening of the alloys and understanding the potential impact of each addition on the reliability of the solder in the final application. Here improvements in thermal, mechanical and metallurgical properties of the new alloy Maxrel Plus are discussed and compared to SAC405. Based on drop shock test, single ball shear test (high temperature storage, PCT and MSL1), thermal cycling test and intermetallics measurement results, we conclude that Maxrel Plus is specially recommended for use in WLCSP.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132363571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Cu wire stitch bond reliability study under high temperature storage","authors":"Wang Miao","doi":"10.1109/EPTC.2015.7412357","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412357","url":null,"abstract":"Copper wire bond has been applied in industry for years and its package reliability is certainly an important subject for researchers and manufacturers. The mechanism of wire bond formation is complicated and a consensus hasn't been reached. Combination of a few theories to hypothesize the whole process of copper wire stitch bond formation on silver plating surface is elaborated in this paper. The key factors determine high temperature aging reliability of a system consists of copper, silver and epoxy mold compound is discussed. Lastly, a case of stitch bond open failure under high temperature storage with copper wire bonded on silver plated copper leadframe package is discussed. Failure analysis is conducted and root cause is identified.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130151907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Study on failure mode and mechanism of bond pad under Cu ball bonding process using wire pull test and finite element modeling","authors":"F. Che, L. Wai, H. Hsiao, T. Chai","doi":"10.1109/EPTC.2015.7412385","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412385","url":null,"abstract":"In this work, wire pull test combined with finite element analysis (FEA) were conducted to investigate failure mode and failure criterion for bond pad reliability assessment under Cu wire bond process. Pull test was conducted for bonded Cu wires with different pull locations changing from the first ball bond to the second wedge bond. Failure forces were recorded and failure site and modes were studied. The effect of pull location on failure mode was observed. Failure modes change from wire neck broken, ball lift, pad peel to wedge broken when pull location is changing from the first bond towards the second bond. Based on wire pull test and FEA simulation results, failure mechanism and failure criterion were developed for different Cu wire bond failure modes. The effects of wire loop height on pull test results and modeling stress were also investigated.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131605291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Substrate opening to increase solder joint reliability and circuit integration","authors":"Lim Teck Guan, Che Faxing","doi":"10.1109/EPTC.2015.7412392","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412392","url":null,"abstract":"A novel solution to reduce the effect of coefficient of thermal expansion (CTE) mismatch between the package and the circuit board is proposed here. In this solution, the circuit board area directly beneath the package is removed to form a patterned opening. It is believed that the opening provide an additional direction for the circuit board expansion. The simulated result showed that the solder reliability of the substrate opening is better than using underfill. Depending on the requirement, the design of the opening such as the shape and dimension can be optimized. For higher circuit integration density, other package or module can be integrated through the opening. The proposed solution is simple as it only requires to form through opening in the circuit board. It does not require the costly underfill process.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"222 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134460625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal cycling reliability analysis of an anisotropic conductive adhesive attached large-area chip with area array configuration","authors":"J. Kiilunen, S. Lahokallio, L. Frisk","doi":"10.1109/EPTC.2015.7412380","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412380","url":null,"abstract":"The reliability of adhesive flip chip attachments was studied. A large-area chip with a great number of contacts was attached onto a flexible polyimide substrate using anisotropic conductive adhesive film (ACF). The test samples were manufactured using various bonding forces and the reliability of the assemblies was examined using a thermal cycling test. Two temperature change rates were used in the cycling test to study the effect of the change rate on the observed failure times and modes. The results show that the ACF flip chip attachment of large-area chips with matrix array interconnections is an applicable technique. Furthermore, a significant increase in the reliability of the assemblies was obtained by increasing the bonding force. However, early failures were observed in all the samples, especially in the outermost adhesive interconnections. Failure analysis performed on the samples exhibiting early failures showed signs of adhesive delamination and silicon chip cracking. No clear differences in the results between the two temperature cycling tests used were observed. However, the faster temperature change rate seemed to cause a higher number of early failures.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115712803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Evaluation of influencing factors on the heavy wire bondability of plasma printed copper structures","authors":"C. Kaestle, T. Losch, J. Franke","doi":"10.1109/EPTC.2015.7412290","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412290","url":null,"abstract":"Power semiconductor devices and systems enable the efficient conversion and management of electrical energy. Power electronic applications range from fewer watts up to several mega- and gigawatts. Driven by a continuous electrification of society, power electronics are not only found in the automotive and energy sector, but also in industrial and lighting applications, as well as consumer electronics. In power electronic devices wire bonding is the established and predominant top-level interconnect technology due to a high process stability and low production costs. Characterized by a great process flexibility it might also be the predominant interconnection technology of coming additive manufactured devices and structures if wire bonding proves to be capable of connecting printed layers that form the basis of additive functionalized and even three-dimensional power device layouts. This paper will therefore display the influencing factors, as well as the possibilities and challenges that come along with the process combination of cold active atmospheric plasma printing with large wire aluminum bonding. For the investigations, copper layers are additively printed on Al2O3 ceramic substrates. Based on the printing parameters the most influential characteristics of the printed layers are derived. The influence and effectiveness of various steps of post processing such as grinding and cleaning are discussed. Last, a production series of 300 μm aluminum wires is bonded on the generated copper layers. The process stability as well as the interconnection quality is evaluated by destructive pull and shear tests and metallographic cross sections.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114964674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fluxless packaging of an implantable medical device for transcorneal electrical stimulation","authors":"Fuliang Le, J. Lo, X. Qiu, S. Lee, Xing Li, C. Tsui, W. Ki","doi":"10.1109/EPTC.2015.7412282","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412282","url":null,"abstract":"Transcorneal electrical stimulation (TcES) is one of the potential therapies to prevent retinal degeneration. This study reports on an implantable medical device for TcES. The regular TcES components, such as stimulator chips, metal wires, electrodes and printed circuit boards (PCBs), are all packaged into the device. The device has a thin-film shape and is soft enough to bend, thus it is placed beneath the cornea without exposure to the outside. The stimulator chip, with the function of generating precise stimulation current to prevent retinal degeneration, is flip bonded onto a flexible PCB using gold studs and thermosonic bonding process. Thermosonic bonding eliminates the use of flux, which is not biocompatible with in-vivo implants. The surfaces of the gold stud bumps are in general non-uniform. Coining is an essential pretreatment of compressing the gold stud bumps against a flat solid surface to obtain much smoother & larger surfaces. This pretreatment helps form high-strength joints between the gold stud bumps and the PCB pads. In the packaging process, underfill is applied in the gaps between the chips and the flexible PCB to enhance the reliability of the gold joints. A compression molding step is subsequently conducted to cover all internal components with a silicone material. The two electrodes, which are made of gold studs, can be exposed by grinding. A coining step is followed to ensure the flatness of the two electrodes.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116898029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}