2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)最新文献

{"title":"Challenges and countermeasure of strip form reflow screening process for flip chip QFN and module package","authors":"Lim Ming Siong, Gan Tek Keong, W. C. Way","doi":"10.1109/EPTC.2015.7412422","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412422","url":null,"abstract":"Solder joint robustness is a major challenge in flip chip packaging. Poor wetting and solder joint crack are the most common manufacturing defects which usually lead to product functional and reliability failure. The risk level is elevated whereby failure is occurred intermittently and only become permanent during SMT process at customer application where thermal mechanical stress induced. The conventional manufacturing quality controls are always applied which include visual inspection during and after die bond, x-ray after encapsulation and tighten test limit. However such controls are not able to screen out all defects effectively especially intermittent failure. Nowadays, reflow screening process has become common in semiconductor packaging as many semiconductor manufacturers found technically that above defects can be aggravated to certain degrees which finally fail during electrical testing. Reflow screening process is widely known to be requirement especially in automotive product's customer. However, we are seeing increasing numbers of consumer product's customer like mobile phone (Samsung) demanded reflow as a mandatory process at all their semiconductor component supplier. Form of semiconductor component undergo reflow become very critical especially miniature package size of QFN which the smallest size down to 1.0mm × 0.6mm × 0.36mm. It is impossible to perform reflow screening process in singulated-unit form base on today test platform limitation. On the other hand, strip form reflow face multiple manufacturing challenges especially for thin Cu lead-frame or premold lead-frame. This paper is to discuss the challenges and countermeasure to setup and implement strip form reflow screening process. High temperature applied during reflow may contribute to SMT pad oxidation or contamination. Influence of pad finishing eg Au / Sn pad might subsequently lead to solder-ability risk. Thus, reflow before plating is proposed. However, during setting up of reflow process, high non-plate rejects (~50%) was encountered on Electroless Nickel Immersion Gold (ENIG) plating package. TGA and FTIR were performed to reveal the hypothesis of decomposition of the mold compound wax to form carbonyl group (-C=O) and subsequently deposited on the SMT pad. Reflow after plating is applied on ENIG package with assessment on solder ability test to mitigate the risk. Due to CTE mismatch of mold compound and base material in strip form, different level of strip deformation which include coil set, crossbow and strip shrinkage were observed for different packages. High strip deformation not only brings to quality concern such as panel crack, bubble trapped, offset saw, panel shrinkage, also at the same time giving difficulties in both lamination and package sawing manufacturing process. Optimizing the strip design during reflow, which including splitting of the strip form to array form and removal of strip metal reel show significant different in strip deformation espe","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117181901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modeling and simulation of the ultrasonic wire bonding process","authors":"T. Meyer, A. Unger, Simon Althoff, W. Sextro, M. Brokelmann, M. Hunstig, K. Guth","doi":"10.1109/EPTC.2015.7412377","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412377","url":null,"abstract":"Ultrasonic wire bonding is an indispensable process in the manufacturing of semiconductor components. It is used for interconnecting the silicon die to e.g. connectors in the housing or to other semiconductors in complex components. In high power applications, such as wind turbines, locomotives or electric vehicles, the thermal and mechanical limits of interconnects made from aluminum are nearing. The limits could be overcome using copper wire bonds, but their manufacturing poses challenges due to the harder material, which leads to increased wear of the bond tools and to less reliable production. To overcome these drawbacks, adaptation of process parameters at runtime is employed. However, the range of parameter values for which a stable process can be maintained is very small, making it necessary to compute suitable parameters beforehand. To this end, and to gain insights into the process itself, the ultrasonic bonding process is modeled. The full model is composed of several partial models, some of which were introduced before. This paper focuses on the modularization of the full model and on the interaction of partial models. All partial models are presented, their interaction is shown and the general outline of the simulation process is given.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128355416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Faraday cage for EMC improvement of electronic devices","authors":"Shailesh Kumar, Rishi Bhooshan, S. Varshney, C. Verma, L. Gideon","doi":"10.1109/EPTC.2015.7412272","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412272","url":null,"abstract":"In conventional packaging there is a considerable scope of noise coupling with external environment. This may cause the device in concern to fail due to EMI and may also cause other electronic device in the vicinity to fail due the electro-magnetic radiations from the device in concern. In order to reduce the coupling between two high frequency signals, providing a ground shield between them is a common practice - both inside the die as well as on the BGA packages. In Lead frame packages, the technique is though limited to extremely small pin packages (6-10 pins) wherein a portion of the flag metal is cut in such a way so as to provide a ground shield between the pins. This technique fails for medium or high pin packages. The only other option is to connect every alternate lead_to ground to reduce coupling noise between the package pins. This reduces the effective number of usable pins and is not desirable. Resultantly, the lead frame packages suffer from low noise immunity for highly sensitive signals, leading to functional failures.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128178819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Electrical transmission characteristics of vertical transition with through silicon vias (TSVs) in 3D die stack","authors":"K. Chang, R. Weerasekera, S. Bhattacharya","doi":"10.1109/EPTC.2015.7412339","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412339","url":null,"abstract":"Two vertical transitions with through silicon vias (TSVs) in 3D die stack are designed and their high frequency electrical characteristics are presented in this paper. The two vertical transitions consist of TSVs for obtaining electrical connection between the die front side and back side. Back side redistribution layer is eliminated in the designs to simplify the fabrication process without sacrificing the electrical performance. Design considerations and guidelines are provided to design high speed TSV structure up to 50 GHz. Different kinds of transmission line interconnects (for instance, microstrip line and coplanar waveguide) are implemented at the input/output extensions for different applications. For both vertical transition designs, the simulated insertion loss is better than 0.65 dB up to 50 GHz while good impedance matching from DC to 50 GHz is obtained with the simulated return loss greater than 14 dB.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127092985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"New decapsulation methods for ICs with Cu and Ag wires","authors":"Michael Obein, Francois Berger, P. Poirier","doi":"10.1109/EPTC.2015.7412398","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412398","url":null,"abstract":"Introduction of Cu and more recently of Ag wires in integrated circuits made the decapsulation more challenging for failure analysts. We made an experiment with the existing techniques we study in the past years and a comparison with the results and the emerging techniques from the last researchs. This study shows that solution has been demonstrated but there is still a place for improvement if we want to have a robust process for all types of ICs.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128917595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enhance TCOB life for wafer level package with a new leadfree solder alloy","authors":"Xueren Zhang, W. Goh, K. Wong, D. Yap, K. Goh","doi":"10.1109/EPTC.2015.7412371","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412371","url":null,"abstract":"Driven by minimized package size, cost as well as performance, wafer level package (WLCSP) is currently one of the fastest growing segments in the semiconductor packaging industry. Not as plastic BGA with a substrate interposer, WLP is a silicon chip directly mounted on printed circuit board (PCB) board. The large CTE(coefficient of thermal expansion) mismatch between silicon and organic leads to very high solder joint stress, which will decrease TCOB(thermal cycling on board) life for solder joints. Thus TCOB life is one of the main challenges on WLCSP, especially with large die. This study is focused on enhancement of TCOB life for WLCSP in the face of increasing die-size requirements. Several WLCSPs with different size are selected as test vehicles. Mechanical simulation has been carried out to understand the TCOB behavior and help to optimize the package design. TCOB test has been done to quantify the real life and to validate the simulation models for current SAC-N solder. To enhance the life margin, especially for large size package, a new Solder SAC-Q has been evaluated. Initial results indicate SAC-Q is showing remarkable TCOB improvement with acceptable drop test performance. Simulation model has been built up to understand the different behavior between SAC-Q and SAC-N. Much lower plastic work in SAC-Q correlates well to its longer life than SAC-N.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130241442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Highly thermal conductive transparent die attach material for LEDs","authors":"Kai Zhang, Jie Li, Xinfeng Zhang, M. Yuen, Lisa Liu, Yuhua Lee, Cheng Sheng Ku, Chuiming Wan, Zhaoming Zeng, Guowei David Xiao","doi":"10.1109/EPTC.2015.7412390","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412390","url":null,"abstract":"Transparent die attach materials (DA) with moderate thermal conductivity without yellowing are preferred for mid-power LEDs, which dominate the LED backlighting and general solid-state lighting markets. A novel DA was developed based on a new kind of silicone base material specifically designed and synthesized. Compared with widely used transparent DA of KER-3000-M2 from Shin-Etsu Chemical Co., Ltd., the newly developed DA has high thermal conductivity of 0.53 W/m-K, low viscosity of 7 Pa-s at 1 s-1, and a transmittance of 97% at wavelength of 450 nm without trading off the good adhesion. Packaged in 0.3 W blue LEDs, the new DA helps achieve around 26% thermal resistance reduction and 7.7% radiometric power improvement.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128831407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Titanium disilicide formation for detection of temperature drift and oxygen leak in rapid thermal processing tool","authors":"N. Sivanantham, C. C. Hoo, L. Hong, Sae Tae Veera","doi":"10.1109/EPTC.2015.7412421","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412421","url":null,"abstract":"In this paper, titanium film thickness in the range of 40nm to 125nm was characterized for optimizing the thickness-temperature combination for titanium disilicide (TiSi2) formation which can be used as a detecting temperature drift. Post silicidation sheet resistance was measured to analyze the integrity of anneal process. Scanning Electron Microscope and X-ray Photoelectron Spectroscopy techniques were employed to validate thickness of titanium film and determine elemental composition respectively. Atomic Force Microscopy was employed for characterizing roughness of the film. This paper recommends a set of process parameters and titanium film thickness for efficiently using TiSi2 sheet resistance for detecting temperature drifts in the window of 600°C to 650°C. Besides, the silicidation process is also shown to be useful in detecting O2 leak in the chamber, utilizing the discoloration of titanium when reacting with oxygen under heat.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126556621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The influence of alloying elements on metastable NiSn4 in Sn-Ag solders on Ni-containing metallizations","authors":"S. Belyakov, C. Gourlay","doi":"10.1109/EPTC.2015.7412427","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412427","url":null,"abstract":"Sn-Ag based solders are a popular Pb-free alternative in consumer electronics and have a relatively long history with a large body of dedicated research. Past research has primarily focused on the formation of interfacial intermetallic (IMC) layers and the growth of ßSn, and little attention has been paid to Ni-containing IMCs that form in the bulk solder when Sn-Ag alloys are soldered to Ni-containing metallizations. The present study illustrates a new phenomenon: formation of metastable NiSn₄ as a primary and a eutectic phase in solder joints between Sn-Ag solders and Ni-containing surface finishes. The metastable NiSn₄ was demonstrated to transform into ßSn and equilibrium Ni₃Sn₄ IMC phase during ageing at 150°C. Impact shear tests suggested a significant drop in solder joint mechanical response when larger than 2μm NiSn₄ crystals were present in the solder bulk. Further exploration of the influence of alloying elements on metastable NiSn₄ in solder joints yielded three scenarios: (i) Au, Pt, Pd and Co promoted NiSn₄ formation and increased its volume fraction by substituting for Ni atoms in NiSn₄; (ii) Bi, In, Fe and Pb additions appeared to have little or no discernible effect on NiSn₄ and (iii) Cu was found to promote equilibrium Ni₃Sn₄ phase formation that replaces metastable NiSn₄ at Cu levels above 0.3wt%.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"163 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115306046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Development of SiC power module using 70μm single metal layer substrates","authors":"Hwang How Yuan, N. Jaafar, Sorono Dexter Velez, Lee Jong Bum, Y. Y. Wei, Daniel Rhee Min Woo","doi":"10.1109/EPTC.2015.7412299","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412299","url":null,"abstract":"While leadframe has come a long way as a cost effective substrate, there is still limitation over its design rule. In this article, the authors have developed and put to test a SiC based PQFN using 70μm single metal layer substrates, allowing further miniaturization and complex design of PQFN. New high temperature EMC with a Tg of 241°C and lead free bismuth silver solder are adopted. Reliability tests and RDS,on results showed that the materials adopted in the development does not degrade the MOSFET's functionality and all samples passed reliability and power cycling tests.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121678970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}