2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)最新文献

{"title":"Room-temperature ultrasonic-bonding characteristics of compliant micro-bump investigated by ex-situ and in-situ measurements","authors":"K. Iwanabe, Kenichi Nakadozono, Y. Senda, T. Asano","doi":"10.1109/EPTC.2015.7412363","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412363","url":null,"abstract":"Room temperature microjoining of Au-Au or Cu-Cu bumps in the air ambient has been achieved by using the cone-shaped bumps with ultrasonic assist. This paper reports bonding mechanism investigated from the results of ex-situ and in-situ measurements. As an ex-situ measurement, we firstly investigate effect of the application of ultrasonic vibration on magnitude of plastic deformation of the compliant bump. We show that \"softening\" of the bumps take place under the application of ultrasonic vibration. Second, change in crystal texture near the bonded interface was analyzed to clarify how the ultrasonic bonding produce bonded interface at room-temperature. As an in-situ measurement, dynamic strain generated under the bonding pad is measured by using a strain gauge made of Si.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"19 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113979466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"RF modeling and optimization of end-launch SMA to trace transition","authors":"H. Zha, Diqun Lu, Wei Wang, F. Lin","doi":"10.1109/EPTC.2015.7412280","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412280","url":null,"abstract":"In this paper, lumped element model of end-launch Sub-Miniature version A (SMA) to trace transition is presented, based on verified scattering-parameters from EM simulation. SMA is mounted on four-layer PCB and standard FR4 is chosen as its dielectric substrate. Close agreement between EM simulation and proposed model is obtained for S-parameters up to 20GHz. Moreover, based on the equivalent circuit, the optimization of impedance discontinuity of this transition is investigated, both return loss and impedance properties are experimentally validated with the improvement.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122666631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Robust packaging solutions through innovative designs in clip-QFN","authors":"Roxanna Samson, Ruby Ann M. Camenforte, Lorraine R. Duldulao","doi":"10.1109/EPTC.2015.7412291","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412291","url":null,"abstract":"The quality and success of a product starts from a right design. Geometry of lead frames and clips are crucial components in manufacturability and long term reliability of clip-QFN packages. Every product has a unique set of component lay-out and configuration; and this doesn't mean outright BOM (bill of material) compatibility for new product built on similar qualified package. Die dimension and component stack up for instance require careful considerations. During design stage, features such as stress relief and geometry should be comprehended. Clip design also indicates the assembly manufacturability of the product. Clip frames must maintain a robust design in adapting to the specific packaging requirement while maintaining the mechanical integrity to withstand multiple assembly operations. Poor designs can lead to reliability issues most notable during thermal cycle testing. This paper will cover the entire clip-QFN design journey, the clip-QFN top defects reduction and elimination that TI Clark is aspiring toward.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122884206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Configurable sintered interconnect (CSI) DAP-less QFN package for high thermal performance application","authors":"M. Nachnani, P. Rogren, Yuhao Sun","doi":"10.1109/EPTC.2015.7412336","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412336","url":null,"abstract":"Smart phones and mobile devices are one of the key drivers of Internet of Things (IOT). Requirements of better power dissipation, higher electrical performance and low cost continue to drive innovation and new technologies in packaging. Using innovative additive manufacturing technology, EoPlex has developed a new type of QFN package that does not use any etched processes for manufacturing. It addresses improvements in electrical performance for single layer packages, with better power dissipation and lower cost than existing solutions.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122885614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improvement of the near short failure through foreign particle reduction in package","authors":"Tee Swee Xian, Hanafi Jonet, A. Hanafi","doi":"10.1109/EPTC.2015.7412417","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412417","url":null,"abstract":"The presence of foreign metal particle inside the encapsulation of IC package can seriously cause a near short failure mechanism. The near short typically formed with two neighbour wires or bond pad with a small spacing. The near short will be degraded to an intermittent contact and finally a short at the early life. Especially with the high pin counts and finer bond pad pitch package, a 8um metal particle can cause the near short phenomena. In this paper, the source of foreign metal particle had been identified using EDX technique. Initial finding show the foreign metal particle consists of Cu, Ag, Fe, Cr, Al elements. It is believe that the source of foreign particles is coming from the raw material and assembly process parts. In order to further understand the presence of the particles from each assembly process steps, a detailed process mapping (mouse trap monitoring) had been carried out to further identified the potential risk area. A total of 3 concepts had been applied to reduce the particles in the package which are prevention of metal particle drop into the package, reduction of the friction between two metals and the 5S control. It was found that by installing the roller bearing at indexer track to minimize the friction between two metals is successfully reduce 93% of the particle burr that will drop off and mold in the package. Avoid metals friction will helps to reduce foreign metal particle to eliminate near short failure.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131615318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"High temperature resistant Ni-Sn transient liquid phase sintering bonding for new generation semiconductor power electronic devices","authors":"Hongliang Feng, Jihua Huang, J Zhang, Xiaodong Zhai, Xingke Zhao, Shuhai Chen","doi":"10.1109/EPTC.2015.7412388","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412388","url":null,"abstract":"This paper presents the microstructural evolution of a Niekel-Tin(Ni-Sn) TLPS process. Ni-Sn power mixture was assembled in a Ni/Ni-Sn/Ni sandwiched structure and sintered in a vacuum furnace using different times at 340°C. The results show that after 180min with slight pressure of 0.1MPa the majority of Sn and Ni in the joint have completely formed intermetallic compounds(IMC) and the jointing layers mainly consists of Ni3Sn4, but not dense enough. With the increase of processing time, a dense microstructure can be observed after 300min. Microstructural characterization revealed the formation joints governed by the interdiffusion of the main constituents. The differential scanning calorimetry(DSC) profiles also show that the melting endothermic peak corresponding to Sn is negligible after 180min at 340°C and the melting event corresponding to the Ni3Sn4 occurs at approximate 798.9°C. Compared to the traditional solding technique, a higher temperature resistance bonding joint can be achieved using the Ni-Sn TLPS bonding at lower bonding temperature.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126998113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Large format encapsulation","authors":"E. Kuah, J. Hao, Yuan Bin, W. Chan, Wu Kai, S. Ho","doi":"10.17265/2328-2223/2016.01.002","DOIUrl":"https://doi.org/10.17265/2328-2223/2016.01.002","url":null,"abstract":"This paper will review the challenges on large format encapsulation with respect to mold cap thickness control, encapsulant impact on moldability such as flow mark and flow mark on final product. Control of mold co-planarity is best performed dynamically during molding, otherwise it would be challenging to obtain good co-planarity within ± 20 μm. Moldability demand such encapsulant coverage with highly viscous material, flow-ability and flow mark are discussed. Warpage control heavily depends on the formulation of the encapsulant and the form of encapsulant, i.e., granular, liquid and sheet.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"29 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133812379","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation of key factors in thermal compression (TCB) NCF bonding process","authors":"Lei Yang, D. Tian, Y. Cheung, Ming Li","doi":"10.1109/EPTC.2015.7412382","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412382","url":null,"abstract":"Electronics with higher Input/Output (I/O) density and smaller package size challenge the fine pitch flip chip technology. Thermal compression bonding combined with pre-applied non-conductive film (TC-NCF) has the advantages of simplifying the process steps, protecting interconnects in situ, avoiding the flux residue and having no concerns of adhesive overflow issue. It is a promising process for fine pitch, thin die flip chip packages. In this study, a series of TC-NCF experiments using two types of NCFs were performed on both Chip-on-substrate (CoS) and Chip-on-chip (CoC) packages. Process factors affecting the bondability of TC-NCF interconnect such as bonding force, heating rate, bonding temperature and wetting time were investigated. The results were addressed from bondability evaluation criterions of solder wetting, NCF voids and solder shape. This investigation can serve as a reference for TC-NCF process development and failure analysis.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"47 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114112872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"COOL substrate for 2.5D assembly","authors":"Charles Lin, Nick Wang, J. Tan","doi":"10.1109/EPTC.2015.7412354","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412354","url":null,"abstract":"System integration with high data transmission often demands packaging solution having fine line routing capability in order to deliver the desired performances with better power and signal integrity. However, while wafer fabrication is advancing at a relentless pace, IC substrate technology has not been able to catch up device's fine feature needs at reasonable cost. This is due mainly to resin materials' poor mechanical stability and equipment limitations of current manufacturing infrastructure. As such, inorganic interposer such as silicon and glass interposers have been investigated intensively with their excellent material properties such as low CTE, high modulus and through-via processing capability. However, even fine feature interposer can meet devices' interconnect needs, most of 2.5D architectures adopt chip-first assembly methodology, which suffers high manufacturing cost due to high yield loss and thus limits their applications only in a very narrow area. This paper will describe an innovative chip-last 2.5D assembly using an integrated substrate namely, Carrier-on-Organic-Laminate (COOL) substrate to address fine pitch interconnection and manufacturing infrastructure issues. Structurally, COOL substrate has an interposer embedded in a build-up laminate and supported by a stiffener. The interposer can be chosen from ceramic, organic, glass, or silicon-based chip carrier depending on device routing density requirements and cost constraint. As interposer/laminate is interconnected by micro-via plating process (a low temperature process and devoid of solder reflow), thermal induced stress and interposer warpage problems can be largely resolved. As such, unlike most conventional 2.5D approaches where chip(s) are attached on an interposer before being assembled on HDI substrate by solder, COOL substrate allows most difficult chip-attachment process as the very last assembly step. In other words, COOL substrate simplifies the entire 2.5D assembly by enabling only one high temperature solder reflow process (e.g., micro-bump thermal compression) on a known good interposer/substrate. From the electrical performance viewpoint, COOL substrate minimizes the large power losses caused by the parasitic resistances and inductance introduced by conventional HDI substrate's plated through holes in core layer. Stiffener in COOL substrate can provide mechanical support and warpage management for the entire board. While the interposer maintains flatness in the central region, the stiffener control the warpage from periphery and this low warp feature allows copper pillar bumps be adopted in flip chip assembly. The paper will illustrate how the COOL substrate can be adapted for conventional flip chip assembly without incurring expensive new equipment and new tooling. Other benefits such as better thermal dissipation pathway and supporting Package-on-Package assembly solution will be described as well.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114545376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enhanced package on package with coreless substrate optimal design evaluation","authors":"V. Lin, K. Liu, N. Kao, D. Jiang","doi":"10.1109/EPTC.2015.7412264","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412264","url":null,"abstract":"Coreless substrate was popularized to develop for Enhanced Package on Package (ePoP) series package to effectively shrink package thickness and provide higher electrical performance. Therefore, in order to achieve those targets, Embedded Trace Substrate (ETS) coreless substrate was approached on bottom FCCSP package of ePoP structure. However, the warpage performance is the critical challenge for ePoP structure, especially on bottom package. This paper will aim to investigate Molding Level Package (MLP) and Bare Die Package (BDP) of ePoP bottom package characteristics with 3 layer and 4 layer ETS coreless substrate by using Finite Element Method (FEM) to find out the major key factors on material property and structure. For the material property, this study will come out the CTE, modulus and Tg material property trend chart of compound, underfill, prepreg (PP) and solder mask. For the structure, there are several parameter studies such as die thickness, prepreg thickness, solder mask thickness and the Cu coverage of 3/4L ETS substrate effect. According to lots simulation work, this study shows MLP structure with optimal material and structure design on 3/4L ETS substrate could pass the warpage criteria at 25C and 260C, but BDP structure may still have warpage risk easily due to no compound material to resist substrate deformation. Based on that, this study keeps studying on the Molded Interconnection System (MIS) substrate for BD structure to make the BDP structure to have no warpage risk. After the evaluation, MLP and BDP structure with ETS or MIS substrate would have no warpage risk under the optimal simulation suggestions and the simulation results show good correlation results with our internal experiment data. Finally, it is successful to apply coreless substrate into novel ePoP series and also can achieve shrinking package thickness and providing higher electrical performance advantages.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114686050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}