2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)最新文献_第9页

Full 300 mm electrical characterization of 3D integration using High Aspect Ratio (10:1) mid-process through silicon vias 使用高纵横比(10:1)通过硅过孔的过程中3D集成的完整300毫米电气特性

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) Pub Date : 2015-12-01 DOI: 10.1109/EPTC.2015.7412323

F. Gaillard, T. Mourier, L. Religieux, D. Bouchu, C. Ribiére, S. Minoret, M. Gottardi, G. Romero, V. Mevellec, C. Aumont

{"title":"Full 300 mm electrical characterization of 3D integration using High Aspect Ratio (10:1) mid-process through silicon vias","authors":"F. Gaillard, T. Mourier, L. Religieux, D. Bouchu, C. Ribiére, S. Minoret, M. Gottardi, G. Romero, V. Mevellec, C. Aumont","doi":"10.1109/EPTC.2015.7412323","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412323","url":null,"abstract":"In this paper, we present an innovative solution to successfully metallize Through Silicon Vias (TSV) with High Aspect Ratio (10:1). These structures represent a key element in the 3D mid-process integration approach. The metallization consists in depositing, respectively, a diffusion barrier and a seed layer, using two different conformal deposition techniques. The technique used for the barrier material is based on a MOCVD TiN process while the second one involves a copper electrografting method. An additional copper Physical Vapor Deposition (PVD) layer is temporarily deposited to fulfill the requested properties and finalize a viable TSV integration on double sided 300mm design architecture. Further electrical characterizations of Kelvin TSVs and daisy chains are obtained. On a first hand, a 33mOhm resistance value is measured for a single 10×100μm via structure. This measurement is consistent with the theoretical value expected for this particular TSV design. On a second hand, contact continuity of up to 754 via chain structures validates the potential viability of this integration architecture for 3D device manufacturing.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129279078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

High performance accelerated test methods for reliability and life time analyses of power electronic packages 电力电子封装可靠性和寿命分析的高性能加速试验方法

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) Pub Date : 2015-12-01 DOI: 10.1109/EPTC.2015.7412396

M. Mueller, J. Franke

{"title":"High performance accelerated test methods for reliability and life time analyses of power electronic packages","authors":"M. Mueller, J. Franke","doi":"10.1109/EPTC.2015.7412396","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412396","url":null,"abstract":"This paper describes and discusses two methods, with which highly accelerated aging tests on power electronics components can be done efficiently and with high performance. On the one hand, an alternative method of thermal shock tests with a liquid ambient medium is described. By the use of liquids as an energy transfer medium with a high heat transfer coefficient, a quick coupling of thermo-mechanical stresses at the interface of the module can be realized. So the test speed increases and the time of testing decreases. Thereby there is a shock load on the assembly even at low temperature amplitudes. In addition, a liquid-based shock system is characterized by high resource efficiency. In order to avoid any spread of the liquid medium through the transfer process of the test samples, the use of the same medium for the cold and the hot reservoir is required. In recent tests Galden® PFPE D02TS with an application range from -97 °C to +165 °C or the silicone oil WACKER® AK 35 with a maximum operating range from -60 °C to +150 °C are identified as the technically most purposeful liquids. This paper also presents a modified power cycling test equipment, with which the thermal and electrical connection of the device under test with different body variants can be realized flexibly. Further up to 20 samples can be tested simultaneously.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130141216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Achieving accurate electro-optical-thermal measurements of high-power LEDs 实现高功率led的精确电光热测量

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) Pub Date : 2015-12-01 DOI: 10.1109/EPTC.2015.7412321

T. K. Law, Fannon Lim, Y. Li, J. Teo, Z. Tai

{"title":"Achieving accurate electro-optical-thermal measurements of high-power LEDs","authors":"T. K. Law, Fannon Lim, Y. Li, J. Teo, Z. Tai","doi":"10.1109/EPTC.2015.7412321","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412321","url":null,"abstract":"High-power Light Emitting Diode (LED) generates significant amount of heat fluxes that can affect the temperature-dependent properties of the device. This self-heating effect can upset the measurement setup and produce inaccurate readings, leading to misinterpretation of results such as electrical and thermal resistances. Optical, electrical and thermal performances of high-power LED packages were analysed under different temperature feedback controls. The results of these experiments demonstrate the importance of the temperature control module in the measurement setup affecting the device's properties such as the series resistance Rs and the thermal resistance Rth. In the electrical current-voltage measurements, the temperature control module cannot control the self-heating effect effectively, resulting in a lower Rs compared to when the measurements are made manually. In transient thermal measurements, it was found that lower Rth values are obtained when the controller operates in closed-loop adaptive temperature control compared to when it operates in open-loop adaptive temperature control. This paper recommends the manual electrical and open-loop thermal measurement methods for accurate parametric LED analyses.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129901822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Impact of mold compound on reliability performance in roughened Ni/Pd/Au-Ag preplated leadframe package 模具化合物对粗化Ni/Pd/Au-Ag预镀引线框封装可靠性性能的影响

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) Pub Date : 2015-12-01 DOI: 10.1109/EPTC.2015.7412428

Wu-Hu Li, Khai Seen Yong, Albert Acuesta, Juergen Schredl

{"title":"Impact of mold compound on reliability performance in roughened Ni/Pd/Au-Ag preplated leadframe package","authors":"Wu-Hu Li, Khai Seen Yong, Albert Acuesta, Juergen Schredl","doi":"10.1109/EPTC.2015.7412428","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412428","url":null,"abstract":"In this study, roughened Ni/Pd/Au-Ag alloy-plated Cu leadframe and two types of mold compounds (A and B) were studied in terms of button shear tests on the leadframe surfaces and package performance after assembly and after reliability stresses. The package reliability stresses include pre-conditioning at Moisture Sensitivity Level 3 (MSL3) with three cycles of reflow at 260 °C (peak temperature) according to the standard for automotive products, followed by 100 cycles of temperature cycling (TC), autoclaving (AC) for 96 hours, and TC for 500 cycles. The results show that the button shear force of Mold Compound A on the leadframe surface is much higher than that of Mold Compound B on the same leadframe surface at room temperature as well as after MSL3 pre-conditioning. The package using Mold Compound A shows positive results after all the stresses stated above, while the package using Mold Compound B shows no delamination after assembly but does show minor delamination after AC for 96 hours and gross delamination after TC for 500 cycles at the bottom side of a die paddle. It is understood that the roughened surface is only on the top side of the leadframe surface and the bottom die paddle surface is the normal surface. Thus, the interface between the bottom die paddle of the leadframe and mold compound is the weakest interface in terms of adhesion, and after stresses it is weakened further and shows delamination. This study shows that the mold compound plays a very critical role in the package reliability in roughened Ni/Pd/Au-Ag pre-plated leadframe packages.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121208712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Silicone soft and transparent layer for wafer-level fabrication of optical applications 硅树脂软透明层，用于光学晶圆级制造

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) Pub Date : 2015-12-01 DOI: 10.1109/EPTC.2015.7412277

Thomas Seldrum, C. Yeakle, Remington Fischer, Maynard G. Hyer, Vincent Delsuc

{"title":"Silicone soft and transparent layer for wafer-level fabrication of optical applications","authors":"Thomas Seldrum, C. Yeakle, Remington Fischer, Maynard G. Hyer, Vincent Delsuc","doi":"10.1109/EPTC.2015.7412277","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412277","url":null,"abstract":"Dow Corning developed a spin-on dielectric polydimethylsiloxane material suitable for wafer-level packaging in optical applications. The product is optically transparent in the visible range and has a very low Young modulus, inducing a low residual stress when applied at a wafer level. The product has been specifically designed for use as a thin protection or passivation layer of devices and it can also be used as permanent bonding adhesive. Specific attention in the formulation of the product was considered in order to minimize the amount of volatiles being released in the processing steps and a volatile-free layer over a broad temperature range is created at the end of the process. In the discussion section of this paper, a first section will explain the processing conditions of this wafer-level packaging solution and the key benefits will be exposed. A second section will present the volatile outgasing study in order to demonstrate that pending proper care is considered in the processing steps, the silicone solution can be used in a manufacturing environment and that a volatile-free layer is created at the end of the process. A third section will deal with the optical properties of this product and the stability after UV exposure will be exposed. The dielectric strength stability of the silicone layer will be investigated in a fourth section, followed by a study of the low mechanical stress induced by this product coated on a silicon wafer. A brief summary of all the benefits brought by this new technology will finally by summarized in the conclusion section.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121283455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impact of backside processing on C-V characteristics of TSV capacitors in 3D stacked IC process flows 三维堆叠IC工艺流程中背面加工对TSV电容器C-V特性的影响

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) Pub Date : 2015-12-01 DOI: 10.1109/EPTC.2015.7412311

J. de Vos, M. Stucchi, A. Jourdain, E. Beyne, Jash Patel, Kath Crook, Mark Carruthers, J. Hopkins, H. Ashraf

引用次数: 3

3D integration technology using W2W direct bonding and TSV for CMOS based image sensors 采用W2W直接键合和TSV的CMOS图像传感器三维集成技术

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) Pub Date : 2015-12-01 DOI: 10.1109/EPTC.2015.7412378

N. Pham, N. Tutunjyan, Danny Volkaerts, Lan Peng, Geraldine Jamison, D. Tezcan

引用次数: 3

Advanced wire bonding technology for Ag wire 先进的银丝键合技术

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) Pub Date : 2015-12-01 DOI: 10.1109/EPTC.2015.7412367

Aashish Shah, T. Rockey, Hui Xu, I. Qin, Wu Jie, O. Yauw, B. Chylak

{"title":"Advanced wire bonding technology for Ag wire","authors":"Aashish Shah, T. Rockey, Hui Xu, I. Qin, Wu Jie, O. Yauw, B. Chylak","doi":"10.1109/EPTC.2015.7412367","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412367","url":null,"abstract":"With the introduction and proliferation of Cu wire bonding, the cost of wire bonding packages is greatly reduced compared to traditional Au wire bonding. Wire bonding is still the most popular interconnect technology and the work horse of the industry. Technology development and innovation in wire bonding has provided new packaging solutions that improve performance and reduce the cost. This paper reviews the pros and cons of each bonding wire type that is being used for ball bonding including Au, Cu, and Ag wire. Although Cu wire is by far the cheapest bonding wire, in certain cases Cu wire is not a viable solution due to either the lack of advanced Cu wire equipment and process or the special requirements of the package. For example, Cu wire bonding has challenges with memory devices that require low loops and thin overhang die. In this case for memory devices, Ag wire is a good alternative that can provide significant cost reduction. This paper further examines the challenges and solutions for Ag wire bonding process including Free Air Ball (FAB) formation, the 1st bond and the 2nd bond. The key developments in ball bonding equipment, process and material to overcome these challenges are discussed. We studied the FAB formation process and studied the effect of cover gas system design, EFO (Electronic Flame Off) current, EFO gap, and other factors that affect the ball formation process. We demonstrate fine pitch capability of Ag wire bonding including 1st bond and 2nd bond using 0.6 mil Ag wire. Both forward bonding processes as well as SSB (Standoff Stitch Bond) are studied using new response based processes. The different wire alloys from 87% Ag to 97% Ag are also studied and compared in order to understand the differences in wire performance.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126603072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

Silicon cap structure development and microassembly for forward tactile sensing in endovascular guidewire intervention 血管内导丝介入前向触觉传感的硅帽结构发展及微装配

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) Pub Date : 2015-12-01 DOI: 10.1109/EPTC.2015.7412324

Ruiqi Lim, E. L. Tan, K. Tan, Weiguo Chen, Ramona B. Damalerio, Ming-Yuan Cheng

引用次数: 0

A low-temperature temporary lamination and laser debonding technology to enable cost-effective fabrication of a through-glass-via (TGV) interposer on a panel substrate 一种低温临时层压和激光脱粘技术，能够经济高效地在面板基板上制造玻璃通孔(TGV)中间层

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) Pub Date : 2015-12-01 DOI: 10.1109/EPTC.2015.7412337

Alvin Lee, Jay Su, Baron Huang, Dongshun Bai, Wen-Wei Shen, Hsiang-Hung Chang, C. Chiang

{"title":"A low-temperature temporary lamination and laser debonding technology to enable cost-effective fabrication of a through-glass-via (TGV) interposer on a panel substrate","authors":"Alvin Lee, Jay Su, Baron Huang, Dongshun Bai, Wen-Wei Shen, Hsiang-Hung Chang, C. Chiang","doi":"10.1109/EPTC.2015.7412337","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412337","url":null,"abstract":"This paper describes a handling process for a thin glass panel, 200 mm × 200 mm × 130 (im, through double-side redistribution layer (RDL) formation to enable cost-effective fabrication of through-glass-via (TGV) interposers. The integration scheme includes lamination of a low-temperature bonding material utilizing a lamination process temperature of less than 100°C to bond a thin (130-μm) glass panel onto a carrier glass panel 700 μm thick. The carrier glass panel is treated with a 150-nm laser release layer prior to lamination of the bonding film and subsequently the thin glass panel. Next, the RDL is formed, and the front side of the thin glass panel undergoes aluminum physical vapor deposition (PVD) and polymeric dielectric material deposition. Then a second carrier glass panel, treated with the laser release material and laminated with bonding film, is bonded on the front side of the thin glass panel. An excimer laser with an x-y scanning stage is rastered across the first carrier to ablate the laser release layer for separation of first carrier. Following laser separation, a solvent cleaning step is performed to remove bonding material from the backside of the thin glass panel. The process of applying metal PVD, lithography, and dielectric material is repeated on the backside of the thin glass panel. Finally, the thin glass panel is mounted to tape, and the second carrier glass panel is released using laser ablation to reveal the front side of the thin glass for solvent cleaning and final inspection. The integration of the dry bonding film, thin glass panel lamination, and selective laser debonding technology in this study will pave the way for realization of panel-level packaging in the near future.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114347273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1