Full 300 mm electrical characterization of 3D integration using High Aspect Ratio (10:1) mid-process through silicon vias

Abstract

In this paper, we present an innovative solution to successfully metallize Through Silicon Vias (TSV) with High Aspect Ratio (10:1). These structures represent a key element in the 3D mid-process integration approach. The metallization consists in depositing, respectively, a diffusion barrier and a seed layer, using two different conformal deposition techniques. The technique used for the barrier material is based on a MOCVD TiN process while the second one involves a copper electrografting method. An additional copper Physical Vapor Deposition (PVD) layer is temporarily deposited to fulfill the requested properties and finalize a viable TSV integration on double sided 300mm design architecture. Further electrical characterizations of Kelvin TSVs and daisy chains are obtained. On a first hand, a 33mOhm resistance value is measured for a single 10×100μm via structure. This measurement is consistent with the theoretical value expected for this particular TSV design. On a second hand, contact continuity of up to 754 via chain structures validates the potential viability of this integration architecture for 3D device manufacturing.