三维堆叠IC工艺流程中背面加工对TSV电容器C-V特性的影响

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC) Pub Date : 2015-12-01 DOI:10.1109/EPTC.2015.7412311

J. de Vos, M. Stucchi, A. Jourdain, E. Beyne, Jash Patel, Kath Crook, Mark Carruthers, J. Hopkins, H. Ashraf

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引用次数: 3

摘要

在本文中，我们描述了在3D堆叠IC工艺流程中仔细选择晶圆背面工艺的重要性。特别地，我们报告了TSV通过中间显示和背面钝化过程对TSV的C-V特性的影响。分析了造成TSV电容C-V异常反转的原因，并给出了避免这种影响的解决方法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Impact of backside processing on C-V characteristics of TSV capacitors in 3D stacked IC process flows

In this paper, we describe the importance of carefully selecting the wafer backside processes in 3D stacked IC process flows. In particular, we report on the impact of TSV Via-middle reveal and backside passivation processes on the C-V characteristic of the TSV. The cause of anomalous C-V inversion of the TSV capacitor is explained and a solution is given to avoid this effect.

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2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)

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