2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)最新文献

{"title":"Evaluation of biodegradable coating on the stiffness control of the polyimide-based probe used in neural devices","authors":"K. Tan, Weiguo Chen, Ramona B. Damalerio, Ruiqi Lim, S. Chungpaiboonpatana, Ming-Yuan Cheng","doi":"10.1109/EPTC.2015.7412287","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412287","url":null,"abstract":"In this work, an assembled and integrated flexible probe array with biodegradable coating for stiffness control is demonstrated. The proposed method will help to overcome the stiffness issue faced by polymeric probe array during insertion into the brain tissue. It is proposed to do coating with biodegradable material to increase the stiffness of the probe shanks. Assembly process is simplified as polymer probe and cable were being monolithically fabricated, only the connector needs to be soldered onto the bonding pads. To enhance the soldering between connector and bonding pads, rigid stiffener is designed at the bonding pads region to provide robust support for soldering process and for insertion process.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127769581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Resolving key manufacturing challenges in flip chip QFN package","authors":"James Raymond Baello, Jason B. Colte, R. Quiazon","doi":"10.1109/EPTC.2015.7412331","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412331","url":null,"abstract":"FC QFN package integrates a flip chip interconnect in a QFN body and combines the electrical efficiency of the flip chip interconnect and thermal efficiency of the QFN package. Other advantages include shorter assembly cycle time vs wirebonded QFN and small chip-to-pkg ratio closest to WCSP in terms of package footprint. The versatility of the flip chip QFN package opens new markets with applications on power management and DC-to-DC converters. Although advantageous as a package, the interconnect and package combination introduces several challenges due to its unique design features. This paper enumerates the manufacturing challenges of flip chip QFN associated with its unique package construction features and their possible solutions to the challenges by selecting the correct materials, defining design rules and performing process optimizations.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127346407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Application of copper nanoparticles as die attachment for high power LED","authors":"Byung Hoon Lee, Mei Zhen Ng, A. Zinn, C. Gan","doi":"10.1109/EPTC.2015.7412383","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412383","url":null,"abstract":"Although lead-free tin-based solders is the dominant material currently used in electronics packaging, gold-based solders or silver nanoparticles pastes are also used in applications where high thermal conductivity between joints are required. In this study, we evaluate the application of copper nanoparticles as a die attach material. The copper nanoparticles have a size less than 20 nm which allows low temperature fusion, an organic passivation layer which prevents spontaneous particle fusion and growth at ambient temperatures, as well as avoiding oxidation before its usage. We studied the mechanical strength of Si chips bonded with the copper nanoparticles paste, and they demonstrate good reliability after thermal aging tests. We then applied the paste to bond commercial LED chips to ceramic substrate, which gives better electrical and optical properties than Au-Sn solders while maintaining the mechanical strength of the joint.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"1727 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114908491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Miniaturization of bio-fluidic package for point-of-care diagnostic","authors":"How Yuan Hwang, Lee Tae Yoon, D. Zhi, Chung Jaehoon, Daniel Rhee Minwoo","doi":"10.1109/EPTC.2015.7412296","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412296","url":null,"abstract":"This paper introduces a new packaging concept that allows miniaturization of bio-fluidic package for micro and nanoparticle separation through dielectrophoresis (DEP). Leaf-shaped spacers were patterned at wafer level using a developmental bio-compatible photoresist through lithography processes, allowing better control of spacer profile and thickness. Interconnects were formed on ITO-coated glass and then flip-chip bonded onto the patterned die. The developed test vehicle, measured 5mm × 5mm, has 9216 electrodes arranged within a total sensor area of 3 mm × 3 mm. Experiments using colloids showed that the test vehicle is able to trap the 15μm suspended beads onto the electrodes.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130317669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Influence of indium and zinc oxide nano-particles on properties of SAC0307-xIn-yZnO lead-free solder paste","authors":"Nadee Mccsathicn, Sawada Makoto, T. Ariga, K. Kanlayasiri","doi":"10.1109/EPTC.2015.7412271","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412271","url":null,"abstract":"The influence of indium (In) and zinc oxide (ZnO) nano-particles on the properties of SAC0307-xIn-yZnO lead-free solder paste was presented in this paper. Solder paste was mixed with indium and zinc oxide nano-particles at various concentrations. The influence of these particles on melting point. wettability and interfacial layer after soldering with copper substrate was investigated. The results showed that the addition of lower levels of indium and zinc oxide nano-particles could reduce the melting temperature of SAC0307. Wettability of the solders on copper substrate in terms of contact angle was obviously decreased with the increase of appropriate indium and zinc oxide nano-particle concentration. The zinc oxide nano-particles affected the thickness value of the intermetallic layer. giving it a lower and more uniform distribution between the solder and copper substrate.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131911649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Thermal management solutions and design guidelines for silicon based photonic integrated modules","authors":"G. Tang, C. Li, Xiaowu Zhang, D. Rhee","doi":"10.1109/EPTC.2015.7412288","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412288","url":null,"abstract":"In this study, thermal design and thermal management for a low-cost photonic integrated circuits (PIC) platform is proposed and analyzed. The involved PIC platform is targeted for various applications including optical communications, optical interconnects, signal processing and sensing. The module considered in this study consists of a rigid PCB made of FR4 material and a silicon photonics ICs platform on which a laser diode chip, a driver chip, and a trans-impedance amplifier (TIA) chip are jointed using solder balls. A kovar case is chosen for the module. For the thermal design and thermal management, two objectives are involved in this study. The first one is to reduce the thermal resistance from junction to ambient and the other one is to reduce the thermal cross talk between the driver/TIA chips and laser source chip. The following accomplishments are achieved in this study. The overall junction to ambient thermal resistance is reduced to a certain level and meets the design target. The thermal cross effect between the driver/TIA chips and the laser source chip is reduced by cutting a slot in the silicon photonic platform and implementing separated heat spreaders for these chips.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134122198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Temperature cycling aging studies of Zn-based solders for high-temperature applications","authors":"M. V. Uvarajan, L. H. Lim, M. Goh, F. L. Ng, W. Pan","doi":"10.1109/EPTC.2015.7412325","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412325","url":null,"abstract":"Power semiconductor packages are prone to reliability issues related to microstructural changes, thermal fatigue and thermo-mechanical stresses during high temperature operation. This paper evaluates the reliability of various Pb-free Zn-Al-based solder alloys used as die-attached solder during thermal cycling aging. Minimal interfacial intermetallic compounds (IMCs) growth was observed after 1500 thermal cycles. However, brittle solder cracks were observed in the solder joint after prolonged thermal cycling aging, with preferential cracks occurring near the edges of the Si die-solder interface and surrounding solder defects such as voids and delaminations. Thermo-mechanical FE simulation shows an increase of stresses of at least 50%-61% for void and delamination in various locations within the solder interface. Simulated stress contour plots concurred with crack initiation sites observed during failure analysis of the thermal cycle aged die-attached leadframes.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"290 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134336113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improving the cleaning process in copper wire bonding by adapting bonding parameters","authors":"Simon Althoff, A. Unger, W. Sextro, Florian Eacock","doi":"10.1109/EPTC.2015.7412402","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412402","url":null,"abstract":"Changing manufacturing technologies or material in well-known processes has to be followed by an adaption of process parameters. In case of the transition from aluminum wire to copper wire in heavy wire bonding, the adaption effort is high due to the strongly different mechanical properties of the wire. One of these adaption aspects, apart from wire material, is the existent oxide layers on wire and substrate. The ductile aluminum oxide is not influencing the bonding process much, because it is supposed to break apart in case of plastic deformation. The lubricating copper oxide layer has to be removed before micro welds can develop. Therefore, in this paper, experiments are carried out at low frequency to determine the friction energy needed to abrade the copper oxide layer of wire and substrate, which is indicated by an increase in the resulting friction coefficient. The friction energy per contact area to remove the interfering layers at low frequency is compared to the real bonding process working at 58 kHz. In addition, a theoretical concept is being described to get a grasp of the occurring mechanism. In the end a proposal is given how to set bonding parameters to get the cleanest surfaces with the installed bond tool.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133378248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Interfacial reaction and reliability of high temperature die attach solders for power electronics","authors":"Lee Jong Bum, How Yuan Hwang, Pan Wei Chih, Rhee Min Woo Daniel","doi":"10.1109/EPTC.2015.7412304","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412304","url":null,"abstract":"Lead-free solder alloys for high temperature applications is required to meet increasing demands for reliable replacements for lead-based alloys. Especially, high temperature solder is required for bonding in power electronics packages where first bonding on a lead-frame is performed at a temperature of about 330 °C. In this study, the SiC based TO-220 power package was developed by applying high temperature endurable material sets which can endure over 220°C device junction temperature. The interfacial reaction and reliability of SiC die attachment on and Ni plated lead frames using Zn-Al based solder was investigated. Zn-Al-Ge solder alloy showed good temperature tolerance after temperature cycle (TC), high temperature storage test whereas Zn-Al-Ge-Mg solder alloy showed failures after TC test.","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"358 14","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132340143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Material and process trends for moving from FOWLP to FOPLP","authors":"T. Braun, S. Voges, M. Topper, M. Wilke, M. Wohrmann, U. Maas, M. Huhn, K. Becker, S. Raatz, J.-U Kim, R. Aschenbrenner, K. Lang, C. O'connor, R. Barr, J. Calvert, M. Gallagher, E. Iagodkine, T. Aoude, A. Politis","doi":"10.1109/EPTC.2015.7412348","DOIUrl":"https://doi.org/10.1109/EPTC.2015.7412348","url":null,"abstract":"Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. The technology offers not only solutions for single chip packaging but also approaches for 3D system integration or RF suitable packaging. Mold embedding for this technology is currently done on wafer level up to 12\"/300 mm size. For higher productivity and therewith lower costs larger mold embedding form factors are forecasted for the near future. Besides increasing wafer sizes up to 450 mm an alternative option would be moving to panel sizes leading to Fan-out Panel Level Packaging (FOPLP). Sizes for the panel could range up to 18\"×24\" or even larger. Increasing the embedding size does not only mean an upscaling of the existing technologies but may lead to a change from using wafer processing infrastructure to the ones used for panels. This is especially true when moving from round wafer sizes to larger rectangular panel formats. Here also new materials and processes have to be taken into account. Materials for reconfigured mold embedding as well as dielectric materials for electrical wiring redistribution are key factors for reliable packaging and proven functionality as required e.g. for RF packaging. For reconfigured mold embedding, compression mold processes are used in combination with liquid, granular or sheet compound. Within this paper the evaluation of panel level compression molding with a target form factor of 24\"×18\"/610×457 mm2 is described for different materials. As basis for the redistribution on top of the mold embedded wafer typically a liquid photo-patternable dielectric polymer material is used and applied by spin coating. For large panel sizes photo-patternable materials are still of interest, these will most likely be used as dry films. These are expected to have advantages concerning processing and cost compared to liquid dielectric materials. Hence, a dry film dielectric material has been selected and evaluated for Fan-out Wafer/Panel Level Packaging. The main criterion for the selection of the thin film polymers is the curing temperature due to the fact that the final polymerization has to be done after the deposition on the molded wafer. Standard PIs and PBOs can therefore not be used because temperatures above 250 °C would damage the molding material. BCB-type materials are below this temperature limit, with cure temperatures as low as 200°C, making them ideal candidates for FOWLP. In addition the electrical properties are paving the way to RF applications. However, regarding the RF performance the inhomogeneous material mix of the package can be a critical issue, because of complex wave propagation phenomena. In order to obtain a proper design an assessment of the RF properties is therefore essential. For material and process evaluation a test vehicle has been designed with focus on material and process evaluation as well as reliability testing. In addition test structures for basic RF characterization have been designed ","PeriodicalId":418705,"journal":{"name":"2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128591028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}